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Decoder apparatus and methods for pre-charging bit lines 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G11C-016/06
출원번호 US-0928059 (2001-08-10)
발명자 / 주소
  • Kurihara, Kazuhiro
  • Yachareni, Santosh K.
출원인 / 주소
  • Advanced Micro Devices, Inc., Fujitsu Limited
대리인 / 주소
    Eschweiler & Associates, LLC
인용정보 피인용 횟수 : 83  인용 특허 : 2

초록

Methods and apparatus are disclosed for reading memory cells in a virtual ground memory core, wherein a memory cell is selected to be read and an adjacent memory cell is precharged so as to mitigate leakage current associated with the adjacent cell. Decoder circuitry and methods are disclosed for se

대표청구항

Methods and apparatus are disclosed for reading memory cells in a virtual ground memory core, wherein a memory cell is selected to be read and an adjacent memory cell is precharged so as to mitigate leakage current associated with the adjacent cell. Decoder circuitry and methods are disclosed for se

이 특허에 인용된 특허 (2)

  1. Hollmer Shane ; Kurihara Kazuhiro, Apparatus and method to characterize the threshold distribution in an NROM virtual ground array.
  2. Eitan Boaz,ILX, Method for initiating a retrieval procedure in virtual ground arrays.

이 특허를 인용한 특허 (83)

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  3. Dadashev,Oleg, Apparatus and methods for multi-level sensing in a memory array.
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  5. Shappir, Assaf, Contact in planar NROM technology.
  6. Chung, Sung-Yong; Liu, Zhizheng; Mizuguchi, Yugi; Wang, Xuguang Alan; He, Yi; Kwan, Ming; Hamilton, Darlene; Lee, Sung-Chul; Wang, Guowei; Leong, Nancy, Controlling AC disturbance while programming.
  7. Chung, Sung-Yong; Liu, Zhizheng; Mizuguchi, Yugi; Wang, Xuguang Alan; He, Yi; Kwan, Ming; Hamilton, Darlene; Lee, Sung-Chul; Wang, Guowei; Leong, Nancy, Controlling AC disturbance while programming.
  8. Kim, Jongoh; Kwon, Yi-Jin; Liu, Cheng-Jye, Decoding method in an NROM flash memory array.
  9. Bloom, Ilan; Eitan, Boaz; Irani, Rustom, Dense non-volatile memory array and method of fabrication.
  10. Maayan, Eduardo, Device to program adjacent storage cells of different NROM cells.
  11. Irani, Rustom; Eitan, Boaz; Bloom, Ilan; Shappir, Assaf, Double density NROM with nitride strips (DDNS).
  12. Betser,Yoram; Maayan,Eduardo; Sofer,Yair, Dynamic matching of signal path and reference path for sensing.
  13. Sofer,Yair; Maayan,Eduardo; Betser,Yoram, Dynamic matching of signal path and reference path for sensing.
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  17. Janai, Meir, Flash memory with optimized write sector spares.
  18. Fastow, Richard; Nazarian, Hagop; Xue, Lei, High read speed memory with gate isolation.
  19. Betser, Yoram; Kushnarenko, Alexander; Dadashev, Oleg, Measuring and controlling current consumption and output current of charge pumps.
  20. Polansky, Yan; Lavan, Avi, Memory array programming circuit and a method for using the circuit.
  21. Forbes, Leonard; Ahn, Kie Y., Memory utilizing oxide nanolaminates.
  22. Forbes, Leonard; Ahn, Kie Y., Memory utilizing oxide nanolaminates.
  23. Forbes, Leonard; Ahn, Kie Y., Memory utilizing oxide-conductor nanolaminates.
  24. Forbes, Leonard; Ahn, Kie Y., Memory utilizing oxide-nitride nanolaminates.
  25. Forbes,Leonard; Ahn,Kie Y., Memory utilizing oxide-nitride nanolaminates.
  26. Forbes,Leonard; Ahn,Kie Y., Memory utilizing oxide-nitride nanolaminates.
  27. Dadashev,Oleg, Method and apparatus for measuring charge pump output current.
  28. Lin,Yung Feng; Lin,Yu Shen, Method and apparatus for reading data from nonvolatile memory.
  29. Kirsch, Howard C., Method and system for accelerating coupling of digital signals.
  30. Kirsch, Howard C., Method and system for accelerating coupling of digital signals.
  31. Cohen, Guy, Method circuit and system for determining a reference voltage.
  32. Cohen,Guy, Method circuit and system for read error detection in a non-volatile memory array.
  33. Nguyen,Hao Thai; Lee,Seungpil; Mui,Man Lung; Khalid,Shahzad; So,Hock; Govindu,Prashanti, Method for current sensing with biasing of source and P-well in non-volatile storage.
  34. Do,Mun Hoe, Method for making mask in process of fabricating semiconductor device.
  35. Kuo, Tung-Cheng, Method for operating non-volatile memory with symmetrical dual-channels.
  36. Maayan, Eduardo; Eitan, Boaz; Lann, Ameet, Method for programming a reference cell.
  37. Maayan,Eduardo; Eliyahu,Ron; Lann,Ameet; Eitan,Boaz, Method for programming a reference cell.
  38. Roehr,Thomas; Willer,Josef, Method for programming multi-bit charge-trapping memory cell arrays.
  39. Atir, Shahar; Dadashev, Oleg; Sofer, Yair; Maayan, Eduardo, Method for reading a memory array with neighbor effect cancellation.
  40. Maayan,Eduardo; Cohen,Guy; Eitan,Boaz, Method for reading non-volatile memory cells.
  41. Nguyen,Hao Thai; Lee,Seungpil; Mui,Man Lung; Khalid,Shahzad; So,Hock; Govindu,Prashanti; Mokhlesi,Nima; Sekar,Deepak Chandra, Method for sensing negative threshold voltages in non-volatile storage using current sensing.
  42. Lusky, Eli; Eitan, Boaz, Method of erasing non-volatile memory cells.
  43. Chang, Yao-Wen; Lu, Tao-Cheng, Method of reading dual-bit memory cell.
  44. Chang, Yao-Wen; Lu, Tao-Cheng, Method of reading dual-bit memory cell.
  45. Eitan, Boaz; Shainsky, Natalie, Method, circuit and device for disturb-control of programming nonvolatile memory cells by hot-hole injection (HHI) and by channel hot-electron (CHE) injection.
  46. Shappir, Assaf; Bloom, Ilan; Eitan, Boaz, Method, circuit and system for erasing one or more non-volatile memory cells.
  47. Shappir,Assaf; Eisen,Shai, Method, circuit and systems for erasing one or more non-volatile memory cells.
  48. Cohen, Guy; Polansky, Yan, Method, system and circuit for programming a non-volatile memory array.
  49. Cohen,Guy, Method, system, and circuit for operating a non-volatile memory array.
  50. Shappir,Assaf; Avni,Dror; Eitan,Boaz, Method, system, and circuit for operating a non-volatile memory array.
  51. Lu,Qiang; Fastow,Richard; Wang,Zhigang, Method, system, and circuit for performing a memory related operation.
  52. Forbes,Leonard, NOR flash memory cell with high storage density.
  53. Eitan, Boaz; Shainsky, Natalie, NROM non-volatile memory and mode of operation.
  54. Forbes, Leonard, Nanocrystal write once read only memory for archival storage.
  55. Eitan,Boaz, Non-volatile memory cell and non-volatile memory devices.
  56. Maayan, Eduardo, Non-volatile memory device and method for reading cells.
  57. Lusky, Eli; Shappir, Assaf; Irani, Rustom; Eitan, Boaz, Non-volatile memory structure and method of fabrication.
  58. Nguyen, Hao Thai; Lee, Seungpil; Mui, Man Lung; Khalid, Shahzad; So, Hock; Govindu, Prashanti, Non-volatile storage using current sensing with biasing of source and P-Well.
  59. Nguyen, Hao Thai; Lee, Seungpil; Mui, Man Lung; Khalid, Shahzad; So, Hock; Govindu, Prashanti; Mokhlesi, Nima; Sekar, Deepak Chandra, Non-volatile storage with current sensing of negative threshold voltages.
  60. Kwon, Young Joon, Nonvolatile memory cells, nonvolatile memory cell arrays including the same, and methods of fabricating the same.
  61. Lusky,Eli; Eitan,Boaz; Cohen,Guy; Maayan,Eduardo, Operating array cells with matched reference cells.
  62. Shappir,Assaf; Eisen,Shai, Partial erase verify.
  63. He, Yi; Runnion, Edward F.; Liu, Zhizheng; Randolph, Mark W.; Hamilton, Darlene G.; Chen, Pauling; Le, Binh, Pre-charge method for reading a non-volatile memory cell.
  64. Abedifard, Ebrahim; Roohparvar, Frankie Fariborz, Preconditioning global bitlines.
  65. Abedifard,Ebrahim; Roohparvar,Frankie Fariborz, Preconditioning global bitlines.
  66. Lusky,Eli; Bloom,Ilan; Shappir,Assaf; Eitan,Boaz, Protection of NROM devices from charge damage.
  67. Mokhlesi, Nima, Read operation for non-volatile storage with compensation for coupling.
  68. Mokhlesi, Nima, Read operation for non-volatile storage with compensation for coupling.
  69. Mokhlesi, Nima, Read operation for non-volatile storage with compensation for coupling.
  70. Mokhlesi, Nima, Read operation for non-volatile storage with compensation for coupling.
  71. Lusky, Eli; Eitan, Boaz, Reading array cell with matched reference cell.
  72. Lusky, Eli; Eitan, Boaz; Cohen, Guy; Maayan, Eduardo, Reading array cell with matched reference cell.
  73. Fastow, Richard M.; Guo, Xin; Park, Sheung-Hee, Reading flash memory.
  74. Le, Binh Quang; Chung, Michael; Chen, Pau-Ling, Refresh scheme for dynamic page programming.
  75. Eitan, Boaz, Secondary injection for NROM.
  76. Le, Binh Q.; Achter, Michael; Cleveland, Lee; Chen, Pauling, Selection circuit for accurate memory read operations.
  77. Kouno, Kazuyuki, Semiconductor memory device.
  78. Kouno, Kazuyuki, Semiconductor memory device.
  79. Okayama, Shota; Matsubara, Ken, Semiconductor storage device having memory cell for storing data by using difference in threshold voltage.
  80. Pelli, Gabriele; Bedarida, Lorenzo; Bartoli, Simone; Bosisio, Giorgio, Sense architecture.
  81. Nguyen, Hao Thai; Mui, Man Lung; Lee, Seungpil; Wang, Chi Ming, Sensing in non-volatile storage using pulldown to regulated source voltage to remove system noise.
  82. He, Yi; Liu, Zhizheng; Randolph, Mark W.; Haddad, Sameer S., System for programming a non-volatile memory cell.
  83. Chen, Chung-Kuang; Chen, Han-Sung; Hung, Chun-Hsiung, Y-decoder and decoding method thereof.
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