초록 ▼

The proposed architecture is integrated onto a Digital Signal Processor (DSP) as a coprocessor to assist in the computation of sum of absolute differences, symmetrical row/column Finite Impulse Response (FIR) filtering with a downsampling (or upsampling) option, row/column Discrete Cosine Transform

The proposed architecture is integrated onto a Digital Signal Processor (DSP) as a coprocessor to assist in the computation of sum of absolute differences, symmetrical row/column Finite Impulse Response (FIR) filtering with a downsampling (or upsampling) option, row/column Discrete Cosine Transform (DCT)/Inverse Discrete Cosine Transform (IDCT), and generic algebraic functions. The architecture is called IPP, which stands for image processing peripheral, and consists of 8 multiply-accumulate hardware units connected in parallel and routed and multiplexed together. The architecture can be dependent upon a Direct Memory Access (DMA) controller to retrieve and write back data from/to DSP memory without intervention from the DSP core. The DSP can set up the DMA transfer and IPP/DMA synchronization in advance, then go on its own processing task. Alternatively, the DSP can perform the data transfers and synchronization itself by synchronizing with the IPP architecture on these transfers. This architecture implements 2-D filtering, symmetrical filtering, short filters, sum of absolute differences, and mosaic decoding more efficiently than the previously disclosed architectures of the prior art.

대표청구항 ▼

The proposed architecture is integrated onto a Digital Signal Processor (DSP) as a coprocessor to assist in the computation of sum of absolute differences, symmetrical row/column Finite Impulse Response (FIR) filtering with a downsampling (or upsampling) option, row/column Discrete Cosine Transform

The proposed architecture is integrated onto a Digital Signal Processor (DSP) as a coprocessor to assist in the computation of sum of absolute differences, symmetrical row/column Finite Impulse Response (FIR) filtering with a downsampling (or upsampling) option, row/column Discrete Cosine Transform (DCT)/Inverse Discrete Cosine Transform (IDCT), and generic algebraic functions. The architecture is called IPP, which stands for image processing peripheral, and consists of 8 multiply-accumulate hardware units connected in parallel and routed and multiplexed together. The architecture can be dependent upon a Direct Memory Access (DMA) controller to retrieve and write back data from/to DSP memory without intervention from the DSP core. The DSP can set up the DMA transfer and IPP/DMA synchronization in advance, then go on its own processing task. Alternatively, the DSP can perform the data transfers and synchronization itself by synchronizing with the IPP architecture on these transfers. This architecture implements 2-D filtering, symmetrical filtering, short filters, sum of absolute differences, and mosaic decoding more efficiently than the previously disclosed architectures of the prior art. t al.; US-5884298, 19990300, Smith, Jr. et al.; US-5891034, 19990400, Bucholz; US-5891157, 19990400, Day et al.; US-5904691, 19990500, Barnett et al.; US-5913685, 19990600, Hutchins, 434/265; US-5915250, 19990600, Jain et al.; US-5920395, 19990700, Schulz; US-5920870, 19990700, Briscoe et al.; US-5921992, 19990700, Costales et al.; US-5954664, 19990900, Seegobin; US-5970499, 19991000, Smith et al., 707/102; US-5997476, 19991200, Brown; US-6003007, 19991200, DiRenzo; US-6009212, 19991200, Miller et al.; US-6083163, 20000700, Wegner et al., 600/429; US-6091930, 20000700, Mortimer et al., 434/118; US-6253210, 20010600, Smith et al., 707/104 registered feature data of the verification object; a separate threshold value identifying device for identifying the individual by whether or not the degree of similarity obtained by the verification results exceeds separate threshold values set to correspond to pre-registered feature data; and a separate threshold value calculation device for calculating said separate threshold values based on a verification score distribution of said feature data extracted from the data showing said physical features of the individual who is the verification source and the corresponding feature data, and the verification score distribution of the feature data extracted from said data showing the physical features of the individual who is the verification source and the non-corresponding feature data, wherein said separate threshold values are set at a median value of a highest score of a degree of resemblance calculated when verifying said feature data extracted from the data showing the physical features of the individual who is the verification source and non-corresponding data, and a lowest score in said verification score distribution which is expected to be obtainable for said feature data extracted from the data showing the physical features of the individual who is the verification source. 4. A personal identification apparatus comprising: an input device for inputting designated data that specifies data showing physical features of an individual and pre-registered feature data of the verification object; a memory device having a feature data memory unit for storing the feature data sets that are extracted from input data showing physical features of the individual and a threshold value data memory unit for storing separate threshold value data sets that are set according to the respective feature data sets; and a data processing device having a feature extraction means for extracting a plurality of feature data from the input data showing physical features of a plurality of individuals input by said input device during registration, a registered features selection means that determines feature data that is to be registered based on verification results between the plurality of feature data, threshold calculating means which calculates separate threshold values by verifying the feature data to be registered against pre-registered feature data and carrying out statistical processing on the verification data, said data processing device storing in the feature data memory unit of said memory device said feature data to be registered and storing in the threshold value data memory unit the separate threshold value data; said data processing device further having verification means for extracting feature data of the verification source from the data in said feature data memory unit showing the physical features of the individual input from the input device during verification, and acceptance determination means which reads from said threshold value data memory unit of the memory device the pre-registered feature data of the verification object based on said designated data, said verification means and said acceptance determination means verifies the feature data of the verification source against said pre-registered feature data of the verification object, identification of the individual being based on comparison results of separate threshold data read from said memory device based on said verification score showing verification results and said designated data. 5. A personal identification apparatus comprising: an input device that inputs designated data that specifies data showing physical features of an individual; a memory device having a feature data memory unit that stores feature data sets that are extracted from input data showing the physical features of the individual and a threshold value data unit that stores separate threshold value data sets that are set according to said respective character data sets; and a