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In a field programmable gate array (FPGA) allowing dynamic reconfiguration in time multiplexing fashion, duplicate copies are configured in a time multiplexing manner which are functionally identical to a primary circuit specified for a predetermined FPGA's application. The primary and duplicate cir

In a field programmable gate array (FPGA) allowing dynamic reconfiguration in time multiplexing fashion, duplicate copies are configured in a time multiplexing manner which are functionally identical to a primary circuit specified for a predetermined FPGA's application. The primary and duplicate circuits are interrogated by a voting circuit which determines the existence of a faulted circuit in order to eliminate the faulted circuit from the operation of the FPGA. In this manner, without physical addition of redundant circuits, fault tolerancy for the FPGA is provided to minimize the cost, weight, volume, heat and energy associated issues of conventional redundance techniques.

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In a field programmable gate array (FPGA) allowing dynamic reconfiguration in time multiplexing fashion, duplicate copies are configured in a time multiplexing manner which are functionally identical to a primary circuit specified for a predetermined FPGA's application. The primary and duplicate cir

In a field programmable gate array (FPGA) allowing dynamic reconfiguration in time multiplexing fashion, duplicate copies are configured in a time multiplexing manner which are functionally identical to a primary circuit specified for a predetermined FPGA's application. The primary and duplicate circuits are interrogated by a voting circuit which determines the existence of a faulted circuit in order to eliminate the faulted circuit from the operation of the FPGA. In this manner, without physical addition of redundant circuits, fault tolerancy for the FPGA is provided to minimize the cost, weight, volume, heat and energy associated issues of conventional redundance techniques. y decomposing the STG to determine all non-trivial strongly connected components of the STG; and instructions for determining when a non-trivial strongly connected component (SCC) represents a bad cycle indicating a problem with the logic design. 17. The computer program product of claim 16 wherein the instructions for determining when the non-trivial SCC represents a bad cycle further comprise instructions for determining when the non-trivial SCC is not in any cycle set. 18. The computer program product of claim 16 wherein the instructions for determining when the non-trivial SCC represents a bad cycle further comprise instructions for determining when the non-trivial SCC intersects compliment sets of all cycle sets. 19. Apparatus for verifying a logic design comprising: means for deriving a state transition graph (STG) for the logic design, the STG comprising a plurality of nodes representing values of state variables in the logic design, and a plurality of edges between nodes describing state transitions; means for recursively decomposing