초록 ▼

A method for metallizing integrated circuits is disclosed. In one aspect, an integrated circuit is metallized by depositing liner material on a substrate followed by one or more metal layers. The liner material is selected from the group of tantalum (Ta), tantalum nitride (TaN), niobium (Nb), niobiu

A method for metallizing integrated circuits is disclosed. In one aspect, an integrated circuit is metallized by depositing liner material on a substrate followed by one or more metal layers. The liner material is selected from the group of tantalum (Ta), tantalum nitride (TaN), niobium (Nb), niobium nitride (NbN), vanadium (V), vanadium nitride (VN), and combinations thereof. The liner material is preferably conformably deposited on the substrate using physical vapor deposition (PVD). The one or more metal layers are deposited on the barrier layer using chemical vapor deposition (CVD), physical vapor deposition (PVD), or a combination of both CVD and PVD.

대표청구항 ▼

1. A device, comprising: a substrate; liner material conformably deposited on the substrate, wherein the liner material is selected from the group consisting of tantalum (Ta), tantalum nitride (TaN), niobium (Nb), niobium nitride (NbN), vanadium (V), vanadium nitride (VN), and combinations there

1. A device, comprising: a substrate; liner material conformably deposited on the substrate, wherein the liner material is selected from the group consisting of tantalum (Ta), tantalum nitride (TaN), niobium (Nb), niobium nitride (NbN), vanadium (V), vanadium nitride (VN), and combinations thereof; and one or more metal layers comprising aluminum conformably deposited over the liner material. 2. The device of claim 1 wherein the substrate has one or more dielectric layers formed thereon. 3. The device of claim 2 wherein the one or more dielectric layers are selected from the group consisting of fluorinated silicate glass (FSG), oxynitride, silicon oxide and combinations thereof. 4. The device of claim 2 wherein the one or more dielectric layers have apertures formed therein. 5. The device of claim 4 wherein the apertures are formed through the one or more dielectric layers to the substrate surface. 6. The device of claim 4 wherein the apertures each have dimensions less than about 1 μm (micrometer). 7. The device of claim 1 wherein the liner material has a thickness in a range of about 50 .ANG. to about 1000 .ANG.. 8. A damascene interconnect, comprising: a substrate; one or more dielectric layers formed on the substrate, wherein the one or more dielectric layers have apertures therein; liner material conformably deposited on the surfaces of the apertures, wherein the liner material is selected from the group consisting of tantalum (Ta), tantalum nitride (TaN), niobium (Nb), niobium nitride (NbN), vanadium (V), vanadium nitride (VN), and combinations thereof; and one or more metal layers comprising aluminum conformably deposited on the liner. 9. The damascene interconnect of claim 8 wherein the one or more dielectric layers are selected from the group consisting of fluorinated silicate glass (FSG), oxynitride, silicon nitride and combinations thereof. 10. The damascene interconnect of claim 8 wherein the apertures are formed through the one or more dielectric layers to the substrate surface. 11. The damascene interconnect of claim 8 wherein the apertures each have dimensions less than about 1 μm (micrometer). 12. The damascene interconnect of claim 8 wherein the liner material has a thickness in a range of about 50 .ANG. to about 1000 .ANG..