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System and method for communicating with an integrated circuit

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G01R-031/28
  • G06F-012/00
출원번호 US-0411815 (1999-10-01)
발명자 / 주소
  • Edwards, David Alan
  • Wright, Stephen James
  • Ramanadin, Bernard
출원인 / 주소
  • STMicroelectronics Limited
대리인 / 주소
    Jorgenson, Lisa K.Morris, James H.
인용정보 피인용 횟수 : 32  인용 특허 : 56

초록

A system and method for communicating with an integrated circuit is provided that allows an integrated circuit to communicate debugging information and system bus transaction information with an external system. The system may include an interface protocol that provides flow control between the inte

대표청구항

A system and method for communicating with an integrated circuit is provided that allows an integrated circuit to communicate debugging information and system bus transaction information with an external system. The system may include an interface protocol that provides flow control between the inte

이 특허에 인용된 특허 (56)

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  46. Macachor Edgar R. (Santa Clara CA), Partially resettable, segmented DMA counter.
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  49. Ayukawa Kazushige (Kokubunji JPX) Watanabe Takao (Fuchu JPX) Nakagome Yoshinobu (Hamura JPX), Semiconductor device capable of concurrently transferring data over read paths and write paths to a memory cell array.
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  53. Warren Robert,GBX, Test access port controller and a method of effecting communication using the same.
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  55. Okumoto Koji (Tokyo JPX) Matsuno Katsumi (Kanagawa JPX) Shiono Toru (Tokyo JPX) Senuma Toshitaka (Tokyo JPX) Fukuda Tokuya (Tokyo JPX) Takada Shinji (Kanagawa JPX), Testing method for electronic apparatus.
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이 특허를 인용한 특허 (32)

  1. Pedersen,Frode Milch, Accessing sequential data in microcontrollers.
  2. Matityahu, Eldad; Shaw, Robert; Carpio, Dennis Angelo Ramirez; Le, Ky Hong; Lee, Dong Su, Arrangement for utilization rate display and methods thereof.
  3. Matityahu, Eldad; Shaw, Robert; Gurfinkel, Shlomo; Hui, Siuman, Arrangements and methods for minimizing delay in high-speed taps.
  4. Zaidi, S. Jauher A.; Ou, Michael; Adams, Lyle E.; Ramlaoui, Hussam I.; Mills, Billy D.; Bhagat, Robin, Chip-core framework for systems-on-a-chip.
  5. Brites, Celso Fernando Veras; Prado, Alex Rocha, Debug architecture for multithreaded processors.
  6. Hopkins, Andrew; McDonald-Maier, Klaus; Howells, Gareth, Device to generate a machine specific identification key.
  7. Agarwala, Manisha; Gill, Maria B. H.; Johnsen, John M., Dynamic data trace output scheme.
  8. Swoboda, Gary L., Emulation export sequence with distributed control.
  9. Swoboda,Gary L., Exporting on-chip data processor trace information with variable proportions of control and data.
  10. Darrington, David L.; McCarthy, Patrick Joseph; Peters, Amanda; Sidelnik, Albert, Fault recovery on a massively parallel computer system to handle node failures without ending an executing job.
  11. Matityahu, Eldad; Shaw, Robert; Carpio, Dennis; Le, Ky, Integrated switch tap arrangement and methods thereof.
  12. Mehr, Jamshid; Savin, Gregory Charles, Interface system for in-circuit emulator.
  13. Hetrick, William A.; Stover, Jeremy Dean; Tiemeyer, Matt, Method and apparatus for debugging protocol traffic between devices in integrated subsystems.
  14. Mehta,Naresh; Bayappu,Parmeshwar Reddy; Bowers,Kyle, Method and apparatus for managing testing in a production flow.
  15. Porterfield, A. Kent, Method of detecting a source strobe event using change detection.
  16. Porterfield, A. Kent, Method of pacing and disconnecting transfers on a source strobed bus.
  17. Draper,Andrew, Methods and apparatus for debugging a system with a hung data bus.
  18. Taniguchi,Masayoshi, Microcomputer, a method for protecting memory and a method for performing debugging.
  19. Kurafuji, Takashi, Microprocessor internally provided with test circuit.
  20. Matityahu, Eldad; Shaw, Robert; Carpio, Dennis; Hui, Siuman; Lian, Wei, Secured network arrangement and methods thereof.
  21. Day,Daniel A., Selective control of test-access ports in integrated circuits.
  22. Whetsel, Lee D.; Haroun, Baher S.; Lasher, Brian J.; Vij, Anjali, Shifting instruction data through IRS of IC TAP and TLM.
  23. McHale,David F; Varma,Rahoul K; Wicks,Marc R; Livesley,Mike; Duncan,Gareth, Storage of trace data within a data processing apparatus.
  24. Harris,Jeremy G, System and method for generating trace data in a computing system.
  25. Eder, Patrik; Lyra, Markus, System and method for processing trace information.
  26. Draper, Andrew, System and methods for debug connectivity discovery.
  27. Whetsel, Lee D.; Haroun, Baher S.; Lasher, Brian J.; Vij, Anjali, Third tap circuitry controlling linking first and second tap circuitry.
  28. Peyravian, Mohammad; Roginsky, Allen; Zunic, Nevenko; Matyas, Jr., Stephen M., Time stamping method using time-based signature key.
  29. Wu, June Yuh, Trace and debug method and system for a processor.
  30. Case, Jerry; Murray, James; Allegrucci, Jean-Didier, Trace buffer for a configurable system-on-chip.
  31. Huang, Chih Tsun; Ho, Yen Ju; Hsieh, Ming Chang, Trace compression method for debug and trace interface wherein differences of register contents between logically adjacent registers are packed and increases of program counter addresses are categorized.
  32. Zaidi,S. Jauher A.; Ou,Michael; Adams,Lyle E.; Ramlaoui,Hussam I.; Mills,Billy D.; Bhagat,Robin, Unidirectional bus architecture for SoC applications.
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