IPC분류정보
국가/구분 |
United States(US) Patent
등록
|
국제특허분류(IPC7판) |
|
출원번호 |
US-0071264
(1998-05-01)
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발명자
/ 주소 |
- Seiber, Charles A.
- Shipman, David A.
- Luchetti, Robert J.
- Draudt, Gregg R.
- Hobson, Phillip M.
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출원인 / 주소 |
- Steelcase Development Corporation
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대리인 / 주소 |
Price, Heneveld, Cooper, DeWitt & Litton
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인용정보 |
피인용 횟수 :
24 인용 특허 :
41 |
초록
▼
A partition system for subdividing a building space includes a spine partition having a horizontal frame member defining a first horizontal row of apertures for supporting a furniture unit, and a floor channel configured to stably engage a floor surface and supporting the partition. The floor channe
A partition system for subdividing a building space includes a spine partition having a horizontal frame member defining a first horizontal row of apertures for supporting a furniture unit, and a floor channel configured to stably engage a floor surface and supporting the partition. The floor channel defines a second horizontal row of apertures corresponding to the first horizontal row of apertures for supporting the furniture unit. A fin partition has an end positioned adjacent a front of the spine partition at an off-module position located between vertical side edges of the spine panel, with a top and bottom of the end attached to selected apertures in the first and second rows of apertures. A method related to the above is also claimed.
대표청구항
▼
A partition system for subdividing a building space includes a spine partition having a horizontal frame member defining a first horizontal row of apertures for supporting a furniture unit, and a floor channel configured to stably engage a floor surface and supporting the partition. The floor channe
A partition system for subdividing a building space includes a spine partition having a horizontal frame member defining a first horizontal row of apertures for supporting a furniture unit, and a floor channel configured to stably engage a floor surface and supporting the partition. The floor channel defines a second horizontal row of apertures corresponding to the first horizontal row of apertures for supporting the furniture unit. A fin partition has an end positioned adjacent a front of the spine partition at an off-module position located between vertical side edges of the spine panel, with a top and bottom of the end attached to selected apertures in the first and second rows of apertures. A method related to the above is also claimed. t is a host bridge. 9. The computer system of claim 8, wherein said host bridge is a Host-to-PCI bridge. 10. The computer system of claim 1, wherein said first arbitration signal is a PHOLD# signal and said second arbitration signal is a PHLDA# signal. 11. A computer system comprising: a first bus; a first bus agent coupled to said first bus, said first bus agent is operable to generate a first arbitration signal; a second bus agent coupled to said first bus; a bus arbitration circuit coupled to said first bus and operable to generate a second arbitration signal, wherein during a transaction initiated by said first bus agent, said second arbitration signal, when asserted, indicates said first bus agent is granted ownership of said first bus, and during a transaction initiated by said second bus agent, said second arbitration signal, when asserted, indicates a first state of a status information, and said second signal, when deasserted, indicates a second state of said status information; and wherein said first bus agent initiates a first transaction when said first arbitration signal and said second arbitration signal are asserted before an address phase, and wherein said second bus agent initiates a second transaction when said first arbitration signal is deasserted and said second arbitration signal is asserted during said address phase. 12. The computer system of claim 11, wherein said address phase occurs during a first click cycle that a FRAME# signal is asserted. 13. The computer system of claim 1, wherein said second bus agent includes a storage device, and wherein during said transaction initiated by said first bus agent, said bus arbitration circuit provides said second arbitration signal in response to said first arbitration signal and after said storage device is flushed. 14. The computer system of claim 1, wherein said first state of said status information indicates a first LOCK# state and said second state of said status information indicates a second LOCK# state. 15. A computer system comprising: a first pair of arbitration transmission lines; a second pair of arbitration transmission lines; an atomic access transmission line; a bus agent; a first bridge; and a second bridge coupled to said first bridge via said first pair of arbitration transmission lines, said second bridge is further coupled to said bus agent via said second pair of arbitration transmission lines and said atomic access transmission line, wherein said first bridge is coupled to receive an atomic access signal via said first pair of arbitration transmission lines and said second bridge is coupled to receive said atomic access signal via said atomic access transmission line. 16. The computer system of claim 15, wherein said first pair of arbitration transmission lines include a PHOLD# line and a PHLDA# line. 17. The computer system of claim 15, wherein said second pair of arbitration transmission lines include a REQ# line and a GNT# line. 18. The computer system of claim 15, wherein said atomic access transmission line includes a LOCK# line. 19. The computer system of claim 15, further comprising a plurality of PCI bus transmission is, wherein said plurality of PCI bus transmission lines is couples to said first bridge, said second bridge, and said PCI agent. 20. The computer system of claim 15, wherein said bus agent is a PCI agent, said first bridge is a PCI-to-ISA expansion bridge, and said second bridge is a host-to-PCI bridge. 21. A method of superimposing status information from a first bridge onto an arbitration signal received by a second bridge, comprising: (a) deasserting, if necessary, a first arbitration signal during at least a first clock cycle; (b) asserting a second arbitration signal during at least said first clock cycle; (c) providing an address phase during at least said first clock cycle; and (d) during at least second clock cycle, deasserting said second arbitration signal to indicate a first state
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