초록 ▼

A Heterojunction Bipolar Transistor (HBT) is provided where the SiGe base region is formed through selective deposition, after the formation of the base electrode layer and the emitter window. A sacrificial oxide layer is deposited between the collector and base electrode. The contact to the SiGe ba

A Heterojunction Bipolar Transistor (HBT) is provided where the SiGe base region is formed through selective deposition, after the formation of the base electrode layer and the emitter window. A sacrificial oxide layer is deposited between the collector and base electrode. The contact to the SiGe base is made at an extrinsic area, underneath the base electrode, after removal of the sacrificial oxide. The SiGe is covered with a temporary oxide layer during further processes, and this protective layer is removed immediately before the deposition of the emitter material. The selective deposition of the SiGe at a relatively late stage of the fabrication process helps insure that the film remains free of the stresses which can degrade electron mobility. A process of fabricating the above-described HBT device is also provided.

대표청구항 ▼

A Heterojunction Bipolar Transistor (HBT) is provided where the SiGe base region is formed through selective deposition, after the formation of the base electrode layer and the emitter window. A sacrificial oxide layer is deposited between the collector and base electrode. The contact to the SiGe ba

A Heterojunction Bipolar Transistor (HBT) is provided where the SiGe base region is formed through selective deposition, after the formation of the base electrode layer and the emitter window. A sacrificial oxide layer is deposited between the collector and base electrode. The contact to the SiGe base is made at an extrinsic area, underneath the base electrode, after removal of the sacrificial oxide. The SiGe is covered with a temporary oxide layer during further processes, and this protective layer is removed immediately before the deposition of the emitter material. The selective deposition of the SiGe at a relatively late stage of the fabrication process helps insure that the film remains free of the stresses which can degrade electron mobility. A process of fabricating the above-described HBT device is also provided. ccording to claim 1 wherein said first conducting layer is polysilicon or amorphous silicon layer and wherein said first conducting layer is deposited to a thickness of between about 500 and 1000 Angstroms. 7. The method according to claim 1 wherein said step of removing said first conducting layer comprises chemical mechanical polishing. 8. The method according to claim 1 wherein said step of recessing said first conducting layer is a dry etch or a wet etch. 9. A method for fabricating a DRAM with capacitor under bit line (CUB) cell in an integrated circuit device comprising: providing a plurality of capacitor node contact junctions and a bit line junction in a semiconductor substrate; forming a node contact plug through a first insulating layer to each of said capacitor node contact junctions and forming a bit line contact plug to said bit line junction; depositing a second insulating layer overlying said node contact plugs and etching openings through said second insulating layer to each of said node contact plugs; conformally depositing a first conducting layer overlying said second insulating layer and within said openings; removing said first conducting layer except where said first conducting layer lies within said openings; recessing said first conducting layer below top of said openings wherein each of said first conducting layers forms a bottom plate electrode of said capacitor; thereafter forming a capacitor dielectric layer overlying said bottom plate electrodes and said second insulating layer wherein said capacitor dielectric layer is formed by: depositing a silicon nitride layer overlying said bottom plate electrodes; and growing a silicon oxide layer overlying said silicon nitride layer; depositing a second conducting layer overlying said capacitor dielectric layer and patterning said second conducting layer and said capacitor dielectric layer to form top capacitor plates overlying each of said bottom plate electrodes to complete said capacitors; depositing a third insulating layer overlying said capacitors and etching an opening through said third and second insulating layers between said capacitors to said bit line contact plug; and filling said opening with a third conducting layer to form a bit line to complete fabrication of said DRAM with CUB cell in said integrated circuit device. 10. The method according to claim 9 wherein said node contact plugs comprise polysilicon. 11. The method according to claim 9 wherein said bit line contact plug comprises polysilicon. 12. The method according to claim 9 wherein said first conducting layer is selected from the group consisting of polysilicon and amorphous silicon and wherein said first conducting layer has a thickness of between about 500 and 1000 Angstroms. 13. The method according to claim 9 wherein said step of removing said first conducting layer comprises chemical mechanical polishing. 14. The method according to claim 9 wherein said step of recessing said first conducting layer is selected from the group consisting of: a dry etch and a wet etch and wherein said first conducting layer is recessed by 1000 to 2000 Angstroms from a top surface of said openings. 15. The method according to claim 9 wherein said step of recessing said first conducting layer comprises: coating a photoresist layer overlying said first conducting layer; exposing said photoresist layer and partially developing away said photoresist layer wherein said photoresist layer remains only within said openings and wherein a top surface of said photoresist layer lies 1000 to 2000 Angstroms below a top surface of said openings; thereafter etching away said first conducting layer where it is not covered by said photoresist layer whereby said first conducting layer is recessed by 1000 to 2000 Angstroms from said top surface of said openings; and removing said photoresist layer. 16. The method according to claim 9 wherein said first conducting layer comprises amorphous si