Method of cleaning a substrate surface using a frozen material
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
H01L-021/302
H01L-021/461
출원번호
US-0863507
(2001-05-22)
발명자
/ 주소
Moore, Scott E.
Doan, Trung Tri
출원인 / 주소
Micron Technology, Inc.
대리인 / 주소
Wells St. John P.S.
인용정보
피인용 횟수 :
1인용 특허 :
7
초록▼
In one aspect, the invention includes a method of treating a surface of a substrate. A mixture which comprises at least a frozen first material and liquid second material is provided on the surface and moved relative to the substrate. In another aspect, the invention encompasses a method of treating
In one aspect, the invention includes a method of treating a surface of a substrate. A mixture which comprises at least a frozen first material and liquid second material is provided on the surface and moved relative to the substrate. In another aspect, the invention encompasses a method of treating a plurality of substrates. A treating member is provided proximate a first substrate, and an initial layer of frozen material is formed over a surface of the treating member. A surface of the first substrate is treated by moving at least one of the treating member and the first substrate relative to the other of the treating member and the first substrate. After the surface of the first substrate is treated, the initial layer of frozen material is removed from over the surface of the treating member. The treating member is then provided proximate another substrate, and the surface of the other substrate is treated by moving at least one of the treating member and the second substrate relative to the other of the treating member and the second substrate.
대표청구항▼
In one aspect, the invention includes a method of treating a surface of a substrate. A mixture which comprises at least a frozen first material and liquid second material is provided on the surface and moved relative to the substrate. In another aspect, the invention encompasses a method of treating
In one aspect, the invention includes a method of treating a surface of a substrate. A mixture which comprises at least a frozen first material and liquid second material is provided on the surface and moved relative to the substrate. In another aspect, the invention encompasses a method of treating a plurality of substrates. A treating member is provided proximate a first substrate, and an initial layer of frozen material is formed over a surface of the treating member. A surface of the first substrate is treated by moving at least one of the treating member and the first substrate relative to the other of the treating member and the first substrate. After the surface of the first substrate is treated, the initial layer of frozen material is removed from over the surface of the treating member. The treating member is then provided proximate another substrate, and the surface of the other substrate is treated by moving at least one of the treating member and the second substrate relative to the other of the treating member and the second substrate. ufacturing a semiconductor integrated circuit device according to claim 1, wherein the metal layer left in the wiring groove in step (d) is a metal wiring of a damascene or dual damascene wiring. 3. A process for manufacturing a semiconductor integrated circuit device according to claim 2, wherein the step (e) is performed prior to a substantial progress of corrosion of the metal layer left in the wiring groove. 4. A process for manufacturing a semiconductor integrated circuit device according to claim 3, wherein the first major surface of the wafer is kept wet from the end of step (d) to the end of step (f). 5. A process for manufacturing a semiconductor integrated circuit device according to claim 4, wherein an anti-corrosion treatment is applied to the metal layer between steps (d) and (e). 6. A process for manufacturing a semiconductor integrated circuit device, comprising the steps of: (a) forming an insulating film over a first major surface of a wafer; (b) forming a wiring groove in the insulating film by patterning the insulating film; (c) forming a metal layer including copper as its principal component, over the insulating film and in the wiring groove; (d) removing the metal layer outside the wiring groove by a chemical mechanical polishing method so as to leave the metal layer in the wiring groove; (e) after step (d), transferring the wafer to a post cleaning portion of a single wafer processing apparatus, while keeping the first major surface of the wafer wet with a water shower; (f) after step (e), performing scrub or brush cleaning to the first major surface of the wafer with a liquid chemical; and then (g) making the first major surface of the wafer dry, wherein steps (d) to (g) are performed in the single wafer processing apparatus, which has light shielding structure keeping an illuminance of the inside of the apparatus 100 lux or less. 7. A process for manufacturing a semiconductor integrated circuit device according to claim 6, wherein the metal layer left in the wiring groove in step (d) is a metal wiring of a damascene or dual damascene wiring. 8. A process for manufacturing a semiconductor integrated circuit device according to claim 7, wherein the step (e) is performed prior to a substantial progress of corrosion of the metal layer left in the wiring groove. 9. A process for manufacturing a semiconductor integrated circuit device according to claim 8, wherein the first major surface of the wafer is kept wet from the end of step (d) to the end of step (f). 10. A process for manufacturing a semiconductor integrated circuit device according to claim 9, wherein an anti-corrosion treatment is applied to the metal layer between steps (d) and (e). 11. A process for manufacturing a semiconductor integrated circuit device, comprising the steps of: (a) forming an insulating film over a first major surface of a wafer; (b) forming a wiring groove in the insulating film by patterning the insulating film; (c) forming a metal layer including copper as its principal component, over the insulating film and in the wiring groove; (d) removing the metal layer outside the wiring groove by a chemical mechanical polishing method so as to leave the metal layer in the wiring groove; (e) after step (d), transferring the wafer to a post cleaning portion of a single wafer processing apparatus; (f) after step (e), performing scrub or brush cleaning to the first major surface of the wafer with a liquid chemical; and then (g) making the first major surface of the wafer dry, wherein steps (d) to (g) are performed in the single wafer processing apparatus, which has light shielding structure keeping an illuminance of the inside of the apparatus 100 lux or less at a portion where step (e) is performed, and step (e) includes the substep of: (i) keeping the first major surface of the wafer wet with a water shower. 12. A process for manufacturing a semiconductor integrated circuit device according to claim 11, whe rein the metal layer left in the wiring groove in step (d) is a metal wiring of a damascene or dual damascene wiring. 13. A process for manufacturing a semiconductor integrated circuit device according to claim 12, wherein the step (e) is performed prior to a substantial progress of corrosion of the metal layer left in the wiring groove. 14. A process for manufacturing a semiconductor integrated circuit device according to claim 13, wherein the first major surface of the wafer is kept wet from the end of step (d) to the end of step (f). 15. A process for manufacturing a semiconductor integrated circuit device according to claim 14, wherein an anti-corrosion treatment is applied to the metal layer between steps (d) and (e). 16. A process for manufacturing a semiconductor integrated circuit device, comprising the steps of: (a) forming an insulating film over a first major surface of a wafer; (b) forming a wiring groove in the insulating film by patterning the insulating film; (c) forming a metal layer including copper as its principal component, over the insulating film and in the wiring groove; (d) removing the metal layer outside the wiring groove by a chemical mechanical polishing method so as to leave the metal layer in the wiring groove; (e) after step (d), transferring the wafer to a post cleaning portion of a single wafer processing apparatus, while keeping the first major surface of the wafer wet with a water shower; (f) after step (e), performing scrub or brush cleaning to the first major surface of the wafer with a liquid chemical; and then (g) making the first major surface of the wafer dry, wherein steps (d) to (g) are performed in the single wafer processing apparatus, which has light shielding structure keeping an illuminance of the inside of the apparatus 100 lux or less at a portion where step (e) is performed. 17. A process for manufacturing a semiconductor integrated circuit device according to claim 16, wherein the metal layer left in the wiring groove in step (d) is a metal wiring of a damascene or dual damascene wiring. 18. A process for manufacturing a semiconductor integrated circuit device according to claim 17, wherein the step (e) is performed prior to a substantial progress of corrosion of the metal layer left in the wiring groove. 19. A process for manufacturing a semiconductor integrated circuit device according to claim 18, wherein the first major surface of the wafer is kept wet from the end of step (d) to the end of step (f). 20. A process for manufacturing a semiconductor integrated circuit device according to claim 19, wherein an anti-corrosion treatment is applied to the metal layer between steps (d) and (e). 21. A process for manufacturing a semiconductor integrated circuit device, comprising the steps of: (a) forming an insulating film over a first major surface of a wafer; (b) forming a wiring groove in the insulating film by patterning the insulating film; (c) forming a metal layer including copper as its principal component, over the insulating film and in the wiring groove; (d) removing the metal layer outside the wiring groove by a chemical mechanical polishing method so as to leave the metal layer in the wiring groove; (e) after step (d), transferring the wafer to a post cleaning portion of a single wafer processing apparatus; (f) after step (e), performing scrub or brush cleaning to the first major surface of the wafer with a liquid chemical; and then (g) making the first major surface of the wafer dry, wherein steps (d) to (g) are performed in the single wafer processing apparatus, which has light shielding structure keeping an illuminance of the inside of the apparatus 100 lux or less at a portion where step (e) is performed and the post cleaning portion, and step (e) includes the substep of: (i) keeping the first major surface of the wafer wet with a water shower. 22. A process for manufacturing a semiconductor integrated circuit device according to claim
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이 특허에 인용된 특허 (7)
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