이 특허를 인용한 특허 (135)

1. Chen, Xiangdong; Dyer, Thomas W.; Settlemyer, Kenneth; Yang, Haining S., CMOS devices with stressed channel regions, and methods for fabricating the same.

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2. Zhu, Huilong; Yang, Baewon, CMOS structures and methods for improving yield.

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3. Zhu, Huilong; Yang, Daewon, CMOS structures and methods for improving yield.

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4. Zhu, Huilong; Yang, Daewon, CMOS structures and methods using self-aligned dual stressed layers.

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5. Zhu,Huilong; Doris,Bruce B.; Chen,Huajie, Dislocation free stressed channels in bulk silicon and SOI CMOS devices by gate stress engineering.

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6. Barnette, Jamaica L.; Remis, Luke D., Dividing a single phase pulse-width modulation signal into a plurality of phases.

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7. Fang, Sunfei; Kim, Jun Jung; Luo, Zhijiong; Ng, Hung Y.; Rovedo, Nivo; Teh, Young Way, Dual stress memory technique method and related structure.

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8. Chidambarrao,Dureseti; Dokumaci,Omer H.; Doris,Bruce B.; Gluschenkov,Oleg; Zhu,Huilong, Dual stressed SOI substrates.

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9. Chidambarrao,Dureseti; Doris,Bruce B.; Gluschenkov,Oleg; Dokumaci,Omer H.; Zhu,Huilong, Dual stressed SOI substrates.

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10. Chidambarrao,Dureseti, Enhanced PFET using shear stress.

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11. Zhu, Huilong; Luo, Zhijiong, FinFET structure with multiply stressed gate electrode.

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12. Chidambarrao, Dureseti, Gate electrode stress control for finFET performance enhancement.

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13. Doris, Bruce B.; Gluschenkov, Oleg G.; Zhu, Huilong, High mobility CMOS circuits.

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14. Doris,Bruce B.; Gluschenkov,Oleg G.; Zhu,Huilong, High mobility CMOS circuits.

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15. Doris,Bruce B.; Gluschenkov,Oleg G.; Zhu,Huilong, High mobility CMOS circuits.

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16. Doris,Bruce B.; Chidambarrao,Dureseti; Ku,Suk Hoon, High performance CMOS device structures and method of manufacture.

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17. Doris,Bruce B.; Chidambarrao,Dureseti; Ku,Suk Hoon, High performance CMOS device structures and method of manufacture.

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18. Doris, Bruce B; Gluschenkov, Oleg G, High performance strained CMOS devices.

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19. Doris,Bruce B.; Gluschenkov,Oleg G., High performance strained CMOS devices.

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20. Chidambarrao, Dureseti; Donaton, Ricardo A.; Henson, William K.; Rim, Kern, High performance stress-enhance MOSFET and method of manufacture.

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21. Chidambarrao, Dureseti; Donaton, Ricardo A.; Henson, William K.; Rim, Kern, High performance stress-enhance MOSFET and method of manufacture.

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22. Chidambarrao, Dureseti; Donaton, Ricardo A.; Henson, William K.; Rim, Kern, High performance stress-enhance MOSFET and method of manufacture.

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23. Chen, Huajie; Chidambarrao, Dureseti; Dokumaci, Omer H., High performance stress-enhanced MOSFETS using Si:C and SiGe epitaxial source/drain and method of manufacture.

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24. Chen, Huajie; Chidambarrao, Dureseti; Dokumaci, Omer H., High performance stress-enhanced MOSFETs using Si:C and SiGe epitaxial source/drain and method of manufacture.

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25. Chen, Huajie; Chidambarrao, Dureseti; Dokumaci, Omer H., High performance stress-enhanced MOSFETs using Si:C and SiGe epitaxial source/drain and method of manufacture.

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26. Chen, Huajie; Chidambarrao, Dureseti; Dokumaci, Omer H., High performance stress-enhanced MOSFETs using Si:C and SiGe epitaxial source/drain and method of manufacture.

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27. Chen,Huajie; Chidambarrao,Dureseti; Dokumaci,Omer H, High performance stress-enhanced MOSFETs using Si:C and SiGe epitaxial source/drain and method of manufacture.

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28. Doris, Bruce B.; Guarini, Kathryn W.; Ieong, Meikei; Narasimha, Shreesh; Rim, Kern; Sleight, Jeffrey W.; Yang, Min, High-performance CMOS SOI devices on hybrid crystal-oriented substrates.

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29. Doris,Bruce B.; Guarini,Kathryn W.; Ieong,Meikei; Narasimha,Shreesh; Rim,Kern; Sleight,Jeffrey W.; Yang,Min, High-performance CMOS devices on hybrid crystal oriented substrates.

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30. Zhu,Huilong; Oldiges,Philip J.; Doris,Bruce B.; Wang,Xinlin; Gluschenkov,Oleg; Chen,Huajie; Zhang,Ying, Hybrid SOI-bulk semiconductor transistors.

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31. Zhu, Huilong; Oldiges, Philip J.; Doris, Bruce B.; Wang, Xinlin; Gluschenkov, Oleg; Chen, Huajie; Zhang, Ying, Hybrid SOI/bulk semiconductor transistors.

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32. Park, Eun-seok; Lee, Jeong-hae; Kim, Young-eil; Kim, Jong-seok; Yoon, Ick-jae; Ryu, Young-ho; Park, Jae-hyun, Line structure and method for manufacturing the same.

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33. Chidambarrao, Dureseti; Dokumaci, Omer H., MOSFET performance improvement using deformation in SOI structure.

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34. Chidambarrao, Dureseti; Dokumaci, Omer H., MOSFET performance improvement using deformation in SOI structure.

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35. Solin, Stuart A.; Wickline, Samuel A.; Newaz, AKM Shah; Wallace, Kirk D., Method and apparatus for high resolution photon detection based on extraordinary optoconductance (EOC) effects.

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36. Solin, Stuart A.; Wickline, Samuel A.; Newaz, Akm Shah; Wallace, Kirk D., Method and apparatus for high resolution photon detection based on extraordinary optoconductance (EOC) effects.

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37. Yang, Haining S.; Zhu, Huilong, Method and apparatus for increase strain effect in a transistor channel.

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38. Yang,Haining S.; Zhu,Huilong, Method and apparatus for increase strain effect in a transistor channel.

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39. Yang,Haining S.; Zhu,Huilong, Method and apparatus to increase strain effect in a transistor channel.

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40. Yang,Haining S.; Zhu,Huilong, Method and structure for controlling stress in a transistor channel.

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41. Steegen, An L.; Yang, Haining S.; Zhang, Ying, Method and structure for forming strained SI for CMOS devices.

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42. Steegen,An L; Yang,Haining S.; Zhang,Ying, Method and structure for forming strained SI for CMOS devices.

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43. Steegen, An L.; Yang, Haining S.; Zhang, Ying, Method and structure for forming strained Si for CMOS devices.

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44. Steegen,An L.; Yang,Haining S.; Zhang,Ying, Method and structure for forming strained Si for CMOS devices.

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45. Yang, Haining S.; Lim, Eng Hua, Method and structure for forming strained devices.

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46. Chidambarrao, Dureseti; Dokumaci, Omer H., Method and structure for improved MOSFETs using poly/silicide gate height control.

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47. Chidambarrao,Dureseti; Dokumaci,Omer H., Method and structure for improved MOSFETs using poly/silicide gate height control.

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48. Chidambarrao, Dureseti; Greene, Brian J., Method and structure for improving device performance variation in dual stress liner technology.

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49. Chidambarrao,Dureseti; Greene,Brian J., Method and structure for improving device performance variation in dual stress liner technology.

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50. Augustine,Godfrey; Partlow,Deborah; Turley,Alfred Paul; Knight,Thomas; Hartman,Jeffrey D., Method for integrating silicon CMOS and AlGaN/GaN wideband amplifiers on engineered substrates.

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51. Chidambarrao,Dureseti; Dokumaci,Omer H., Method for reduced N+ diffusion in strained Si on SiGe substrate.

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52. Chidambarrao,Dureseti; Dokumaci,Omer H., Method for reduced N+ diffusion in strained Si on SiGe substrate.

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53. Chidambarrao,Dureseti; Dokumaci,Omer H., Method for reduced N+ diffusion in strained Si on SiGe substrate.

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54. Belyansky,Michael P.; Doris,Bruce B.; Gluschenkov,Oleg, Method of fabricating mobility enhanced CMOS devices.

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55. Chen, Huajie; Chidambarrao, Dureseti; Holt, Judson R.; Ouyang, Qiqing C.; Panda, Siddhartha, Method of forming a cross-section hourglass shaped channel region for charge carrier mobility modification.

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56. Chen,Xiaomeng; Jeng,Shwu Jen; Kim,Byeong Y.; Nayfeh,Hasan M., Method of making a semiconductor structure.

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57. Cheng,Kangguo; Chidambarrao,Dureseti, Method of manufacturing a strained silicon on a SiGe on SOI substrate.

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58. Chidambarrao,Dureseti; Dokumaci,Omer H., Method of manufacturing strained dislocation-free channels for CMOS.

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59. Yang, Haining S.; Panda, Siddhartha, Method to increase strain enhancement with spacerless FET and dual liner process.

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60. Guarin, Fernando; Hostetter, Jr., J. Edwin; Rauch, III, Stewart E.; Wang, Ping-Chuan; Yang, Zhijian J., Methodology for recovery of hot carrier induced degradation in bipolar devices.

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61. Belyansky, Michael P.; Doris, Bruce B.; Gluschenkov, Oleg G., Mobility enhanced CMOS devices.

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62. Adam, Thomas N.; Chidambarrao, Dureseti, Mobility enhancement in SiGe heterojunction bipolar transistors.

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63. Solin, Stuart A.; Wallace, Kirk D.; Wickline, Samuel A.; Hughes, Michael S., Multifunctional nanoscopy for imaging cells.

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64. Solin, Stuart A.; Wallace, Kirk D.; Wickline, Samuel A.; Hughes, Michael S., Multifunctional nanoscopy for imaging cells.

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65. Solin, Stuart A.; Wallace, Kirk D.; Wickline, Samuel A.; Hughes, Michael S., Multifunctional nanoscopy for imaging cells.

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66. Chidambarrao,Dureseti; Dokumaci,Omer H.; Gluschenkov,Oleg G., NFETs using gate induced stress modulation.

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67. Brosnan, Michael J., Non-resonant antennas embedded in wireless peripherals.

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68. Barnette, Jamaica L.; Clemo, Raymond M., Operating a DC-DC converter.

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69. Barnette, Jamaica L.; Clemo, Raymond M., Operating a DC-DC converter.

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70. Barnette, Jamaica L., Operating a DC-DC converter including a coupled inductor formed of a magnetic core and a conductive sheet.

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71. Barnette, Jamaica L., Operating and manufacturing a DC-DC converter.

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72. Barnette, Jamaica L., Operating and manufacturing a DC-DC converter.

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73. Cheng, Kangguo; Divakaruni, Ramachandra, Patterned strained semiconductor substrate and device.

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74. Cheng, Kangguo; Divakaruni, Ramachandra, Patterned strained semiconductor substrate and device.

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75. Cheng, Kangguo; Divakaruni, Ramachandra, Patterned strained semiconductor substrate and device.

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76. Cheng,Kangguo; Divakaruni,Ramachandra, Patterned strained semiconductor substrate and device.

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77. Zhu,Huilong; Doris,Bruce B.; Mocuta,Dan M., Protecting silicon germanium sidewall with silicon for strained silicon/silicon mosfets.

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78. Chidambarrao, Dureseti; Mocuta, Anda C.; Mocuta, Dan M.; Radens, Carl, Pseudomorphic Si/SiGe/Si body device with embedded SiGe source/drain.

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79. Chidambarrao, Dureseti; Mocuta, Anda C.; Mocuta, Dan M.; Radens, Carl, Pseudomorphic Si/SiGe/Si body device with embedded SiGe source/drain.

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80. Beintner,Jochen; Bronner,Gary B.; Divakaruni,Ramachandra; Kim,Byeong Y., Raised STI process for multiple gate ox and sidewall protection on strained Si/SGOI structure with elevated source/drain.

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81. Chidambarrao,Dureseti, Rotational shear stress for charge carrier mobility modification.

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82. Deshpande, Sadanand V.; Doris, Bruce B.; Rausch, Werner A.; Slinkman, James A., STI stress modification by nitrogen plasma treatment for improving performance in small width devices.

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83. Deshpande,Sadanand V.; Doris,Bruce B.; Rausch,Werner A.; Slinkman,James A., STI stress modification by nitrogen plasma treatment for improving performance in small width devices.

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84. Chen, Xiangdong; Yang, Haining S., Semiconductor device structure having enhanced performance FET device.

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85. Arnold, John C.; Chidambarrao, Dureseti; Li, Ying; Malik, Rajeev; Narasimha, Shreesh; Panda, Siddhartha; Tessier, Brian L.; Wise, Richard, Semiconductor device structure having low and high performance devices of same conductive type on same substrate.

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86. Chen, Xiaomeng; Jeng, Shwu-Jen; Kim, Byeong Y.; Nayfeh, Hasan M., Semiconductor structure having undercut-gate-oxide gate stack enclosed by protective barrier material.

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87. Zhu, Huilong; Greene, Brian J.; Chidambarrao, Dureseti; Freeman, Gregory G., Semiconductor-on-insulator structures including a trench containing an insulator stressor plug and method of fabricating same.

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88. Barnette, Jamaica L.; Evans, Douglas I.; Totten, Brian C., Sensing current of a DC-DC converter.

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89. Chidambarrao, Dureseti; Dokumaci, Omer H.; Rengarajan, Rajesh; Steegen, An L., Silicide proximity structures for CMOS device performance improvements.

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90. Chidambarrao, Dureseti; Dokumaci, Omer H.; Gluschenkov, Oleg, Silicon device on SI:C-OI and SGOI and method of manufacture.

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91. Chidambarrao, Duresti; Dokumaci, Omer H.; Gluschenkov, Oleg G., Silicon device on Si: C-oi and Sgoi and method of manufacture.

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92. Chidambarrao, Dureseti; Dokumaci, Omer H.; Gluschenkov, Oleg G., Silicon device on Si:C SOI and SiGe and method of manufacture.

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93. Chidambarrao, Dureseti; Dokumaci, Omer H.; Gluschenkov, Oleg G., Silicon device on Si:C-OI and SGOI and method of manufacture.

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94. Chidambarrao,Dureseti; Dokumaci,Omer H.; Gluschenkov,Oleg G., Silicon device on Si:C-OI and SGOI and method of manufacture.

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95. Ajmera, Atul C.; Baiocco, Christopher V.; Chen, Xiangdong; Gao, Wenzhi; Teh, Young Way, Spacer and process to enhance the strain in the channel with stress liner.

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96. de Souza, Joel P.; Hamaguchi, Masafumi; Ozcan, Ahmet S.; Sadana, Devendra K.; Saenger, Katherine L.; Wall, Donald R., Strain preserving ion implantation methods.

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97. Chan, Kevin K.; Chu, Jack O.; Rim, Kern; Shi, Leathen, Strained Si MOSFET on tensile-strained SiGe-on-insulator (SGOI).

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98. Chan,Kevin K.; Chan,Jack Q; Rim,Kern; Shi,Leathen, Strained Si MOSFET on tensile-strained SiGe-on-insulator (SGOI).

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99. Chan,Kevin K.; Chu,Jack O.; Rim,Kern; Shi,Leathen, Strained Si MOSFET on tensile-strained SiGe-on-insulator (SGOI).

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100. Chan,Kevin K.; Chu,Jack O.; Rim,Kern; Shi,Leathen, Strained Si MOSFET on tensile-strained SiGe-on-insulator (SGOI).

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101. Chidambarrao, Dureseti; Dokumaci, Omer H.; Gluschenkov, Oleg G.; Zhu, Huilong, Strained Si on multiple materials for bulk or SOI substrates.

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102. Chidambarrao,Dureseti; Dokumaci,Omer H.; Gluschenkov,Oleg G.; Zhu,Huilong, Strained Si on multiple materials for bulk or SOI substrates.

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103. Chidambarrao,Dureseti; Dokumaci,Omer H., Strained dislocation-free channels for CMOS and method of manufacture.

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104. Doris,Bruce B.; Chidambarrao,Dureseti; Ieong,MeiKei; Mandelman,Jack A., Strained finFET CMOS device structures.

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105. Chidambarrao,Dureseti; Dokumaci,Omer H.; Gluschenkov,Oleg G., Strained finFETs and method of manufacture.

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106. Cheng,Kangguo; Chidambarrao,Dureseti, Strained silicon on a SiGe on SOI substrate.

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107. Chidambarrao, Dureseti; Dokumaci, Omer H., Strained silicon on relaxed sige film with uniform misfit dislocation density.

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108. Bryant, Andres; Ouyang, Qiqing; Rim, Kern, Strained-silicon CMOS device and method.

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109. Bryant,Andres; Ouyang,Qiqing; Rim,Kern, Strained-silicon CMOS device and method.

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110. Chidambarrao, Dureseti; Henson, William K.; Rim, Kern; Wille, William C., Stress engineering using dual pad nitride with selective SOI device architecture.

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111. Chidambarrao,Dureseti; Henson,William K.; Rim,Kern; Wille,William C., Stress engineering using dual pad nitride with selective SOI device architecture.

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112. Zhu, Huilong; Wang, Jing, Stress-generating shallow trench isolation structure having dual composition.

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113. Zhu, Huilong; Wang, Jing, Stress-generating shallow trench isolation structure having dual composition.

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114. Zhu, Huilong; Wang, Jing, Stress-generating shallow trench isolation structure having dual composition.

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115. Zhu, Huilong; Greene, Brian J.; Chidambarrao, Dureseti; Freeman, Gregory G., Stress-generating structure for semiconductor-on-insulator devices.

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116. Zhu, Huilong; Greene, Brian J.; Chidambarrao, Dureseti; Freeman, Gregory G., Stress-generating structure for semiconductor-on-insulator devices.

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117. Doris,Bruce B.; Belyansky,Michael P.; Boyd,Diane C.; Chidambarrao,Dureseti; Gluschenkov,Oleg, Stressed semiconductor device structures having granular semiconductor material.

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118. Doris,Bruce B; Belyansky,Michael P; Boyd,Diane C; Chidambarrao,Dureseti; Gluschenkov,Oleg, Stressed semiconductor device structures having granular semiconductor material.

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119. Zhu,Huilong; Doris,Bruce B.; Oldiges,Philip J.; Ieong,Meikei; Yang,Min; Chen,Huajie, Structure and method for manufacturing planar strained Si/SiGe substrate with multiple orientations and different stress levels.

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120. Zhu,Huilong; Doris,Bruce B., Structure and method for manufacturing strained FINFET.

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121. Zhu,Huilong; Doris,Bruce B., Structure and method for manufacturing strained FINFET.

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122. Chan,Victor W. C.; Lee,Yong M.; Yang,Haining, Structure and method of applying stresses to PFET and NFET transistor channels for improved performance.

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123. Cabral, Jr.,Cyril; Doris,Bruce B.; Kanarsky,Thomas S.; Liu,Xiao H.; Zhu,Huilong, Structure and method to generate local mechanical gate stress for MOSFET channel mobility modification.

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124. Cabral, Jr.,Cyril; Doris,Bruce B.; Kanarsky,Thomas S.; Liu,Xiao H.; Zhu,Huilong, Structure and method to generate local mechanical gate stress for MOSFET channel mobility modification.

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125. Yang,Haining S.; Zhu,Huilong, Structure and method to induce strain in a semiconductor device channel with stressed film under the gate.

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126. Chen,Xiangdong; Yang,Haining S., Structure and method to optimize strain in CMOSFETs.

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127. Yang, Haining; Li, Wai-Kin, Structure and method to use low k stress liner to reduce parasitic capacitance.

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128. Cheng,Kangguo; Chidambarrao,Dureseti; Divakaruni,Rama; Gluschenkov,Oleg G., Structure of vertical strained silicon devices.

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129. Zhu,Hiulong; Bedell,Steven W.; Doris,Bruce B.; Zhang,Ying, Structures and methods for making strained MOSFETs.

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130. Zhu,Huilong; Doris,Bruce B.; Chen,Huajie, Structures and methods for manufacturing of dislocation free stressed channels in bulk silicon and SOI CMOS devices by gate stress engineering with SiGe and/or Si:C.

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131. Zhu, Huilong; Doris, Bruce B.; Chen, Huajie, Structures and methods for manufacturing of dislocation free stressed channels in bulk silicon and SOI MOS devices by gate stress engineering with SiGe and/or Si:C.

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132. Zhu,Huilong, Structures and methods for manufacturing p-type MOSFET with graded embedded silicon-germanium source-drain and/or extension.

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133. Bedell,Stephen W.; Domenicucci,Anthony G.; Fogel,Keith E.; Leobandung,Effendi; Sadana,Devendra K., Ultra-thin, high quality strained silicon-on-insulator formed by elastic strain transfer.

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134. Bedell,Stephen W.; Domenicucci,Anthony G.; Fogel,Keith E.; Leobandung,Effendi; Sadana,Devendra K., Ultra-thin, high quality strained silicon-on-insulator formed by elastic strain transfer.

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135. Zhu, Huilong; Luo, Zhijiong, finFET structure with multiply stressed gate electrode.

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