초록 ▼

The present invention is directed to a system for anterior fixation of the spine that utilizes an elongated fixation plate. The plating system stabilizes the spine and promotes fusion and incorporation of a graft or implant in a portion of the spinal column. In one aspect of the invention, the fixat

The present invention is directed to a system for anterior fixation of the spine that utilizes an elongated fixation plate. The plating system stabilizes the spine and promotes fusion and incorporation of a graft or implant in a portion of the spinal column. In one aspect of the invention, the fixation plate has a first end with a pair of holes. Bone screws extend through the holes to rigidly secure the plate to a first vertebra. The second end of the plate is provided with a pair of slots through which bone screws extend for engagement with a second vertebra. The screws extending through the slots are translatable in the slot to maintain compression of the spinal column portion. The plating system includes a retainer assembly that prevents screw back out. Methods and instruments relating to the plating system are also described.

대표청구항 ▼

The present invention is directed to a system for anterior fixation of the spine that utilizes an elongated fixation plate. The plating system stabilizes the spine and promotes fusion and incorporation of a graft or implant in a portion of the spinal column. In one aspect of the invention, the fixat

The present invention is directed to a system for anterior fixation of the spine that utilizes an elongated fixation plate. The plating system stabilizes the spine and promotes fusion and incorporation of a graft or implant in a portion of the spinal column. In one aspect of the invention, the fixation plate has a first end with a pair of holes. Bone screws extend through the holes to rigidly secure the plate to a first vertebra. The second end of the plate is provided with a pair of slots through which bone screws extend for engagement with a second vertebra. The screws extending through the slots are translatable in the slot to maintain compression of the spinal column portion. The plating system includes a retainer assembly that prevents screw back out. Methods and instruments relating to the plating system are also described. tching means; and a second output node providing said second voltage via said switching means. 6. A power source voltage conversion circuit for converting a first voltage into a second voltage, having control means for controlling provision and non-provision of the second voltage, and capable of being exchanged by the control means between continuous and intermittent operation modes for continuously and intermittently providing the second voltage respectively, the power source voltage conversion circuit including: switching means integrated with components constituting said power source voltage conversion circuit; an output node directly providing said second voltage bypassing said switching means; and an input node connected to ground via said switching means. 7. The power source voltage conversion circuit according to claim 5 or 6, wherein said switching means goes into the connection state when said power source voltage conversion circuit operates in the continuous operation mode, and moves into the non-connection state in the intermittent operation mode. 8. A power source system comprising: the power source voltage conversion circuit according to claim 5; a capacitor inserted between the second output node of said power source voltage conversion circuit and ground; and a driven device powered by the second voltage supplied from the first output node of said power source voltage conversion circuit. 9. A power source system comprising: the power source voltage conversion circuit according to claim 6; a capacitor inserted between said output node and said input node; and a driven device powered by the second voltage supplied from the output node of said power source voltage conversion circuit. 10. A driven device powered by a voltage supplied from an external source having: switching means integrated with components constituting said driven device, and an output node for outputting said supplied voltage via said switching means, said switching means coupled to said driven device such that said switching means does not cause a reduction in the level of the voltage supplied to said driven device when said switching means is in a closed state. 11. A driven device powered by a voltage supplied from an external source having: switching means integrated with components constituting said driven device, and an input node connected to ground via said switching means, said switching means coupled to said driven device such that said switching means does not cause a reduction in the level of the voltage supplied to said driven device when said switching means is in a closed state. 12. The driven device according to claim 10 or 11, wherein: said driven device is driven by a continuous operation mode, where an external source continuously provides a voltage, and an intermittent operation mode, where the external source intermittently provides the voltage; and said switching means moves into a connection state during the continuous operation mode of said driven device and moves into a non-connection state during the intermittent operation mode of said driven device. 13. A power source system having: a power source voltage conversion circuit for converting a first voltage into a second voltage, having control means for controlling provision and non-provision of the second voltage, and capable of being exchanged by the control means between continuous and intermittent operation modes for continuously and intermittently providing the second voltage respectively; the driven device according to claim 10; and a capacitor inserted between the output node of said driven device and ground. 14. A power source system comprising: a power source voltage conversion circuit for converting a first voltage into a second voltage, having an output node providing the second voltage and control means for controlling provision and non-provision of the second voltage, and capable of being exchanged by the con trol means between continuous and intermittent operation modes for continuously and intermittently providing the second voltage respectively; the driven device according to claim 11 powered by the second voltage supplied from the output node of said power source voltage conversion circuit; and a capacitor inserted between the output node of said power source voltage conversion circuit and the input node of said driven device. 15. A semiconductor integrated circuit comprising: a power source voltage conversion circuit for converting a first voltage into a second voltage, having control means for controlling provision and non-provision of the second voltage, and capable of being exchanged by the control means between continuous and intermittent operation modes for continuously and intermittently providing the second voltage respectively; a driven device powered by the second voltage supplied from said power source voltage conversion circuit; switching means integrated with components constituting said power source voltage conversion circuit and said driven device; a first output node for directly outputting the second voltage converted by said power source voltage conversion circuit; and a second output node for outputting the second voltage converted in said power source voltage conversion circuit via said switching means; said switching means coupled to said driven device such that said switching means does not cause a reduction in the level of the voltage supplied to said driven device when said switching means is in a closed state. 16. A semiconductor integrated circuit comprising: a power source voltage conversion circuit for converting a first voltage into a second voltage, having control means for controlling provision and non-provision of the second voltage, and capable of being exchanged by the control means between continuous and intermittent operation modes for continuously and intermittently providing the second voltage respectively; a driven device powered by the second voltage supplied from said power source voltage conversion circuit; switching means integrated with components constituting said power source voltage conversion circuit and said driven device; an output node for directly outputting the second voltage converted by said power source voltage conversion circuit; and an input node connected to ground via said switching means; said switching means coupled to said driven device such that said switching means does not cause a reduction in the level of the voltage supplied to said driven device when said switching means is in a closed state. 17. The semiconductor integrated circuit according to claim 15 or 16, wherein said switching means moves into a connection state during the continuous operation mode of said power source voltage conversion circuit, and moves into a non-connection state during the intermittent operation mode of said driven device. 18. A power source system having the semiconductor integrated circuit according to claim 15 and a capacitor inserted between the second output node of said power source voltage conversion circuit and ground. 19. A power source system having the semiconductor integrated circuit according to claim 16 and a capacitor inserted between the output node and the input node of said power source voltage conversion circuit. 20. A chip capacitor having first, second and third connection nodes, the chip capacitor having: a capacitor having electrodes one of which is connected to the first connection node; switching means integrated with said capacitor having one terminal serially connected to the other electrode of said capacitor, and the other terminal connected to the second connection node; and a control node serving as said third connection node for controlling the opening/closing of said switching means. 21. A power source system comprising: a power source voltage conversion circuit for converting a first voltage into a second voltage, h aving an output node providing the second voltage and control means for controlling provision and non-provision of the second voltage, and capable of being exchanged by the control means between continuous and intermittent operation modes for continuously and intermittently providing the second voltage respectively; a driven device powered by the second voltage supplied from said power source voltage conversion circuit; and the chip capacitor according to claim 20, wherein one of said first and second connection node is connected to the output node of said power source voltage conversion circuit and the other of said first and second connection node is connected to ground. 22. The power source system, driven device or semiconductor integrated circuit according to claim 1, 8, 9, 10, 11, 13, 14, 15, 16, 18, 19 or 21, wherein said driven device is a cellphone having a speech mode driven by the continuous operation mode of said power source voltage conversion circuit, and a standby mode driven by the intermittent operation mode of said power source voltage conversion circuit. 23. A voltage control method for supplying a voltage to drive a driven device, comprising the steps of: using first and second capacitors connected to said driven device in parallel; providing a voltage to said driven device by providing a voltage to both first and second capacitors during a continuous operation mode in which the voltage is continuously provided to said driven device; and interrupting the voltage supplied to the first capacitor and providing the voltage only to the second capacitor when providing the voltage to said driven device during an intermittent operation mode in which the voltage is intermittently provided to said driven device. ising: a. a PBIAS line for controlling a p-channel transistor; b. an NBIAS line for controlling an n-channel transistor, c. a transistor for pulling up the PBIAS line; d. a transistor for pulling down the PBIAS line; e. a transistor for pulling up the NBIAS line; f. a transistor for pulling down the NBIAS line; and g. a circuit for disabling the bias voltage generator and thereby pulling the PBIAS line to a logic one voltage level and the NBIAS line to a logic zero voltage level; h. wherein the circuit for disabling the bias voltage generator comprises: a node for supplying a positive supply voltage to the transistors for pulling up the PBIAS line and the NBIAS line; a node for supplying a ground voltage to the transistors for pulling down the PBIAS line and the NBIAS line; a voltage supply terminal for providing a positive supply voltage; a transistor for connecting the voltage supply terminal to the node for supplying a positive supply voltage to the transistors for pulling up the PBIAS line and the NBIAS line; a transistor for connecting the voltage supply terminal to the PBIAS line; and a memory cell controlling the transistor for connecting the voltage supply terminal to the node for supplying a positive supply voltage and the transistor for connecting the voltage supply terminal to the PBIAS line, wherein the memory cell turns on one and only one of the transistor for connecting the voltage supply terminal to the node for supplying a positive supply voltage and the transistor for connecting the voltage supply terminal to the PBIAS line. 12. A programmable bias-voltage generator adapted to provide first and second bias-voltage levels to respective first and second transistor control terminals of a differential amplifier, the differential amplifier producing an amplified differential output signal in response to a changing digital input signal, the bias-voltage generator comprising: a. a first bias line connected to the first transistor control terminal and adapted to convey the first bias-voltage level; b. a second bias line connected to the second transistor control terminal and adapted to convey the second bias-voltage level; and c. at least one of a programmable pull-up circuit or a programmable pull-down circuit connected to the first bias line; d. wherein the first bias-voltage level remains stable with changes in the digital input signal. 13. The programmable bias-voltage generator of claim 12, wherein the differential amplifier provides the differential output signal across first and second differential output terminals, expressing a logic one as a first current traveling in a first direction between the first and second differential output terminals and expressing a logic zero as a second current traveling in a second direction between the first and second differential output terminals. 14. The programmable bias-voltage generator of claim 13, wherein the first and second currents are proportional to the first bias-voltage level. 15. The programmable bias-voltage generator of claim 12, wherein the first transistor control terminal is the gate of a first transistor and the second transistor control terminal is the gate of a second transistor. 16. The programmable bias-voltage generator of claim 15, wherein the first transistor operates in saturation. 17. The programmable bias-voltage generator of claim 12, wherein the at least one of a programmable pull-up circuit or a programmable pull-down circuit connected to the first bias line is adapted to produce at least two bias-voltage levels on the first bias line, and wherein none of the at least two bias-voltage levels are power-supply voltage levels. 18. The programmable bias-voltage generator of claim 12, further comprising at least one of a second programmable pull-up circuit or a second programmable pull-down circuit connected to the second bias line, wherein the second, bias-voltage level remains stable with changes in the digital input signal. 19. The programmable bias-voltage generator of claim 18, further comprising at least one of a third programmable pull-up circuit or a third programmable pull-down circuit connected to the second bias line, wherein the second bias-voltage level remains stable with changes in the digital input signal. 4/337; US-4745803, 19880500, Haavasoja, 073/170.26; US-5384715, 19950100, Lytton, 702/012; US-5497100, 19960300, Reiser et al., 324/643; US-5835053, 19981100, Davis, 342/022 e direction of current flowing through the meter, the rate at which energy is being consumed by the load and blanking the disk analog display as an indication when the meter has completed measurement of one energy consumption unit. 16. A method in accordance with claim 15 wherein the disk analog display includes a series of segments that illuminate and said step of displaying comprises the step of illuminating at least one segment to indicate the direction of current flowing through the meter and the rate at which energy is being consumed by the load. 17. A method in accordance with claim 16 wherein said step of illuminating at least one segment comprises the step of illuminating a series of segments to indicate the direction of current flowing through the meter and the rate at which energy is being consumed by the load. 18. A method in accordance with claim 17 wherein said step of illuminating a series of segments comprises illuminating a series of segments in a pre-set sequence. 19. A method in accordance with claim 18 wherein said pre-set sequence comprises a repetitive pattern. 20. A method in accordance with claim 18 wherein said step of illuminating a series of segments in a pre-set sequence comprises: illuminating a first segment when approximately 70% of a predetermined energy consumption unit is measured; illuminating a second segment when approximately 80% of a predetermined energy consumption unit is measured; illuminating a third segment when approximately 90% of a predetermined energy consumption unit is measured; and blanking the first, second, and third segments when approximately 100% of an energy consumption unit is measured.