초록 ▼

A method for making electrical contacts to device regions in a semiconductor substrate, and the resulting structure, is presented. A first set of borderless contacts is initially formed. This first set of contacts is then contacted by a second series of smaller, upper-level contacts. The second set

A method for making electrical contacts to device regions in a semiconductor substrate, and the resulting structure, is presented. A first set of borderless contacts is initially formed. This first set of contacts is then contacted by a second series of smaller, upper-level contacts. The second set of contacts also contact the gate of the device. The structure which results has a form wherein there are stacked contacts to the diffusion layer, and a single level contact to the device gate. The structure further provides local interconnectability over gate structures.

대표청구항 ▼

1. A method of fabricating a semiconductor device, comprising the steps of: defining a gate stack and a diffusion stack on a substrate; forming insulative sidewall spacers abutting the gate stack and the diffusion stack; forming a source/drain region in the substrate; depositing a conformal ni

1. A method of fabricating a semiconductor device, comprising the steps of: defining a gate stack and a diffusion stack on a substrate; forming insulative sidewall spacers abutting the gate stack and the diffusion stack; forming a source/drain region in the substrate; depositing a conformal nitride barrier over the gate stack and the diffusion stack; depositing a first insulative layer over the nitride barrier and first planarizing said first insulative layer; after sad first planarizing, forming a first contact, said first contact extending through both the first insulative layer and the nitride barrier to reach the diffusion stack; second planarizing said first insulative layer and said first contact; after said second planarizing, depositing a second insulative layer upon said first insulative layer and said first contact; forming a second contact, said second contact extending through the second insulative layer to the first contact; forming a third contact extending through the second insulative layer, the first insulative layer, and the nitride barrier, to the gate stack; after forming said second contact and third contact, planarizing said second insulative layer; depositing a third insulative layer upon said planarized second insulative layer; and forming wiring layers including fourth contacts, said fourth contacts extending from the top of the third insulative layer to the second and third contacts; and wherein an area which will contain the gate stack and an area which will contain the diffusion stack each contain a hard-mask consisting of an oxide-nitride-oxide laminar structure. 2. The method of claim 1, wherein chemical mechanical polishing is used for said first planarizing and said second planarizing. 3. The method of claim 1, wherein said first contact and said second contact are comprised of tungsten. 4. The method of claim 1, wherein said first contact and said second contact are comprised of polysilicon. 5. The method of claim 1, further comprising: said first contact having a first cross-sectional area; said second contact having a second cross-sectional area; and wherein the cross-sectional area of said second contact is smaller than the cross-sectional area of said first contact. 6. The method of claim 1, wherein the first contact above the diffusion stack is a self-aligned contact.