초록 ▼

A JOI structure and cell layout including at least one patterned gate stack region present atop a semiconductor substrate, said semiconductor substrate having source/drain diffusion regions of opposite dopant polarity abutting each other present therein, said source/drain diffusion regions are prese

A JOI structure and cell layout including at least one patterned gate stack region present atop a semiconductor substrate, said semiconductor substrate having source/drain diffusion regions of opposite dopant polarity abutting each other present therein, said source/drain diffusion regions are present atop an insulating layer, said insulating layer not being present beneath said at least one patterned gate stack region. An alternative JOI structure and cell layout of the present invention includes at least one patterned gate stack region present atop a semiconductor substrate, said semiconductor substrate containing at least a conductive region other than source/drain diffusion regions present atop an insulating layer embedded therein, said insulating layer not being present beneath said at least one patterned gate stack region, wherein said conductive region is in contact with vertical sidewalls of source/drain extension regions present in said semiconductor substrate, beneath said at least one patterned gate stack region.

대표청구항 ▼

A JOI structure and cell layout including at least one patterned gate stack region present atop a semiconductor substrate, said semiconductor substrate having source/drain diffusion regions of opposite dopant polarity abutting each other present therein, said source/drain diffusion regions are prese

A JOI structure and cell layout including at least one patterned gate stack region present atop a semiconductor substrate, said semiconductor substrate having source/drain diffusion regions of opposite dopant polarity abutting each other present therein, said source/drain diffusion regions are present atop an insulating layer, said insulating layer not being present beneath said at least one patterned gate stack region. An alternative JOI structure and cell layout of the present invention includes at least one patterned gate stack region present atop a semiconductor substrate, said semiconductor substrate containing at least a conductive region other than source/drain diffusion regions present atop an insulating layer embedded therein, said insulating layer not being present beneath said at least one patterned gate stack region, wherein said conductive region is in contact with vertical sidewalls of source/drain extension regions present in said semiconductor substrate, beneath said at least one patterned gate stack region. ion on said flat portion in this order, said buffer layer is provided on said flat portion and on side surfaces of said ridge portion in said cladding layer, and said second semiconductor layer comprises a current blocking layer formed on said buffer layer. 4. The semiconductor device according to claim 3, wherein the thickness of said buffer layer is not less than 20 .ANG. nor more than 500 .ANG.. 5. The semiconductor device according to claim 1, wherein said first semiconductor layer comprises an active layer, a cladding layer having a flat portion and a ridge portion on said flat portion, and a current blocking layer provided on the flat portion and on side surfaces of the ridge portion in said cladding layer, and said buffer layer is provided on an upper surface of said ridge portion of said cladding layer and on said current blocking layer. 6. The semiconductor device according to claim 5, wherein the thickness of said buffer layer is not less than 20 .ANG. nor more than 150 .ANG.. 7. The semiconductor device according to claim 5, wherein a cap layer is further provided between the upper surface of said ridge portion and said buffer layer. 8. The semiconductor device according to claim 1, wherein said nitride based semiconductor is an III group nitride based semiconductor containing at least one of gallium, aluminum, indium, thallium, and boron. 9. The semiconductor device according to claim 8, wherein said nitride based semiconductor composing said buffer layer contains aluminum, and the composition ratio of said aluminum in said buffer layer is more than zero and less than 0.7.