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Output buffer with compensated slew rate and delay control 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H03K-019/0175
출원번호 US-0024884 (2001-12-18)
발명자 / 주소
  • Yin, Ming
출원인 / 주소
  • Sun Microsystems, Inc.
대리인 / 주소
    Paradice, III, William L.M & P, LLP
인용정보 피인용 횟수 : 48  인용 특허 : 6

초록

A circuit includes a drive transistor coupled between an output and a first potential, a constant current circuit coupled between the gate of the drive transistor and a second potential, and a compensation circuit coupled between the gate of the drive transistor and the first potential. The constant

대표청구항

A circuit includes a drive transistor coupled between an output and a first potential, a constant current circuit coupled between the gate of the drive transistor and a second potential, and a compensation circuit coupled between the gate of the drive transistor and the first potential. The constant

이 특허에 인용된 특허 (6)

  1. Chow Hwang-Cherng,TWX ITX 310 ; Huang Chen-Yi,TWX ; Wu Tain-Shun,TWX, High and low speed output buffer with controlled slew rate.
  2. Partovi Hamid (Westborough MA) Van Buskirk Michael A. (San Jose CA), Output buffer arrangement for reducing chip noise without speed penalty.
  3. Ranjan Nalini ; Yang Henry, Output buffer circuit and method that compensate for operating conditions and manufacturing processes.
  4. Penza Luigi (Vimercate ITX) Timineri Calogero (Milan ITX), Output buffer current slew rate control integrated circuit.
  5. Singh Gajendra P., Process compensated output driver with slew rate control.
  6. Lui Henry Y. (San Jose CA) Cheung Sammy S. Y. (Pleasanton CA), Variable slew control for output buffers.

이 특허를 인용한 특허 (48)

  1. Lee, Dong-Uk, Apparatus and method for outputting data of semiconductor memory apparatus.
  2. Lee, Dong-Uk, Apparatus and method for outputting data of semiconductor memory apparatus.
  3. Dadashev, Oleg; Betser, Yoram; Maayan, Eduardo, Apparatus and methods for multi-level sensing in a memory array.
  4. Kushnarenko, Alexander, Circuit and method for powering up an integrated circuit and an integrated circuit utilizing same.
  5. Jung,Young Hee; Kang,Sang Seok, Circuit with fuse and semiconductor device having the same circuit.
  6. Shappir, Assaf, Contact in planar NROM technology.
  7. Wing, Choy Kwok, Current-compensated CMOS output buffer adjusting edge rate for process, temperature, and Vcc variations.
  8. Yi, Jun; Ou, Xuechun, DC-DC converter with temperature, process and voltage compensated dead time delay.
  9. Bloom, Ilan; Eitan, Boaz; Irani, Rustom, Dense non-volatile memory array and method of fabrication.
  10. Maayan, Eduardo, Device to program adjacent storage cells of different NROM cells.
  11. Irani, Rustom; Eitan, Boaz; Bloom, Ilan; Shappir, Assaf, Double density NROM with nitride strips (DDNS).
  12. Huang, Hung-Yu, Driving circuit with slew-rate enhancement circuit.
  13. Betser,Yoram; Maayan,Eduardo; Sofer,Yair, Dynamic matching of signal path and reference path for sensing.
  14. Sofer,Yair; Maayan,Eduardo; Betser,Yoram, Dynamic matching of signal path and reference path for sensing.
  15. Yen, Andrew, I/O buffer with variable conductivity.
  16. Jang, Seong-Jin, Line driver circuit having means for stabilizing output signal.
  17. Betser, Yoram; Kushnarenko, Alexander; Dadashev, Oleg, Measuring and controlling current consumption and output current of charge pumps.
  18. Polansky, Yan; Lavan, Avi, Memory array programming circuit and a method for using the circuit.
  19. Dadashev,Oleg, Method and apparatus for measuring charge pump output current.
  20. Betser,Yoram; Sofer,Yair; Maayan,Eduardo, Method circuit and system for compensating for temperature induced margin loss in non-volatile memory cells.
  21. Maayan, Eduardo; Eitan, Boaz; Lann, Ameet, Method for programming a reference cell.
  22. Maayan,Eduardo; Eliyahu,Ron; Lann,Ameet; Eitan,Boaz, Method for programming a reference cell.
  23. Lusky, Eli; Eitan, Boaz, Method of erasing non-volatile memory cells.
  24. Klein, Christian; McDonald, II, James J., Method of reducing the propagation delay and process and temperature effects on a buffer.
  25. Eitan, Boaz; Shainsky, Natalie, Method, circuit and device for disturb-control of programming nonvolatile memory cells by hot-hole injection (HHI) and by channel hot-electron (CHE) injection.
  26. Shappir, Assaf; Bloom, Ilan; Eitan, Boaz, Method, circuit and system for erasing one or more non-volatile memory cells.
  27. Shappir,Assaf; Eisen,Shai, Method, circuit and systems for erasing one or more non-volatile memory cells.
  28. Cohen, Guy; Polansky, Yan, Method, system and circuit for programming a non-volatile memory array.
  29. Cohen,Guy, Method, system, and circuit for operating a non-volatile memory array.
  30. Shappir,Assaf; Avni,Dror; Eitan,Boaz, Method, system, and circuit for operating a non-volatile memory array.
  31. Eitan, Boaz; Shainsky, Natalie, NROM non-volatile memory and mode of operation.
  32. Eitan,Boaz, Non-volatile memory cell and non-volatile memory devices.
  33. Maayan, Eduardo, Non-volatile memory device and method for reading cells.
  34. Lusky, Eli; Shappir, Assaf; Irani, Rustom; Eitan, Boaz, Non-volatile memory structure and method of fabrication.
  35. Lusky,Eli; Eitan,Boaz; Cohen,Guy; Maayan,Eduardo, Operating array cells with matched reference cells.
  36. Pan, Dong; Silvestri, Paul, Output buffer and method having a supply voltage insensitive slew rate.
  37. Pan, Dong; Silvestri, Paul, Output buffer and method having a supply voltage insensitive slew rate.
  38. Pan,Dong; Silvestri,Paul, Output buffer and method having a supply voltage insensitive slew rate.
  39. Suzuki,Toyoki, Output buffer circuit.
  40. Chen, Yi-Jan Emry; Liu, Pang-Jung; Jiang, Jyun-Ping; Wu, Tsung-Yu, Output buffer circuit with enhanced slew rate.
  41. Huang, Hung-Yu; Chang, Chin-Tien, Output buffer with slew-rate enhancement output stage.
  42. Janssen, Hendrikus Johannes, Output drive comprising an improved control circuit.
  43. Shappir,Assaf; Eisen,Shai, Partial erase verify.
  44. Menegoli,Paolo; Sawtell,Carl K., Process insensitive voltage reference.
  45. Lusky,Eli; Bloom,Ilan; Shappir,Assaf; Eitan,Boaz, Protection of NROM devices from charge damage.
  46. Eitan, Boaz, Secondary injection for NROM.
  47. Pan,Dong; Janzen,Leel S., Temperature-compensated output buffer.
  48. Ku, Ja-Nam; Kim, Cheong-Worl; Min, Young-Hoon; Lee, Dong-Hyun; Song, Il-Jong, Ultra-low-power level shifter, voltage transform circuit and RFID tag including the same.
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