$\require{mediawiki-texvc}$
  • 검색어에 아래의 연산자를 사용하시면 더 정확한 검색결과를 얻을 수 있습니다.
  • 검색연산자
검색연산자 기능 검색시 예
() 우선순위가 가장 높은 연산자 예1) (나노 (기계 | machine))
공백 두 개의 검색어(식)을 모두 포함하고 있는 문서 검색 예1) (나노 기계)
예2) 나노 장영실
| 두 개의 검색어(식) 중 하나 이상 포함하고 있는 문서 검색 예1) (줄기세포 | 면역)
예2) 줄기세포 | 장영실
! NOT 이후에 있는 검색어가 포함된 문서는 제외 예1) (황금 !백금)
예2) !image
* 검색어의 *란에 0개 이상의 임의의 문자가 포함된 문서 검색 예) semi*
"" 따옴표 내의 구문과 완전히 일치하는 문서만 검색 예) "Transform and Quantization"

특허 상세정보

Devices and methods with programmable logic and digital signal processing regions

국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판) H03K-019/177   
미국특허분류(USC) 326/041; 326/038; 326/039; 326/040; 708/625; 708/650; 708/505
출원번호 US-0955645 (2001-09-18)
발명자 / 주소
출원인 / 주소
대리인 / 주소
    Fish & Neave
인용정보 피인용 횟수 : 227  인용 특허 : 15
초록

A programmable logic integrated circuit device ("PLD") includes programmable logic and a dedicated (i.e., at least partly hard-wired) digital signal processing region for performing or at least helping to perform digital signal processing tasks that are unduly inefficient to implement in the more general-purpose programmable logic and/or that, if implemented in the programmable logic, would operate unacceptably or at least undesirably slowly. The digital signal processing region may include multiple digital signal processing stages. The digital signal pr...

대표
청구항

A programmable logic integrated circuit device ("PLD") includes programmable logic and a dedicated (i.e., at least partly hard-wired) digital signal processing region for performing or at least helping to perform digital signal processing tasks that are unduly inefficient to implement in the more general-purpose programmable logic and/or that, if implemented in the programmable logic, would operate unacceptably or at least undesirably slowly. The digital signal processing region may include multiple digital signal processing stages. The digital signal pr...

이 특허에 인용된 특허 (15)

  1. Jiang Shao-Kun ; Wong Roney S. ; Peter-Song Seungyoon. Computational structure having multiple stages wherein each stage includes a pair of adders and a multiplexing circuit capable of operating in parallel. USP2000066078941.
  2. New Bernard J.. Field programmable gate array with distributed gate-array functionality. USP1999025874834.
  3. Tavana Danesh ; Yee Wilson K. ; Trimberger Stephen M.. Integrated circuit with field programmable and application specific logic areas. USP1998105825202.
  4. John Anthony Schadt. Integrated circuit with standard cell logic and spare gates. USP2002066404226.
  5. Steele Randy C. (Southlake TX). Logic block for programmable logic devices. USP1992075128559.
  6. Schultz David P. ; Young Steven P. ; Hung Lawrence C.. Method and structure for reading, modifying and writing selected configuration memory cells of an FPGA. USP2001076255848.
  7. Telikepalli Anil L. N.. Multiplier circuit design for a programmable logic device. USP1998055754459.
  8. New Bernard J.. Multiplier fabric for use in field programmable gate arrays. USP2000116154049.
  9. Chan Andrew K. (Palo Alto CA) Birkner John M. (Portola Valley CA) Chua Hua-Thye (Los Altos Hills CA). Programmable application specific integrated circuit and logic cell therefor. USP1992065122685.
  10. Cliff Richard G. (Milpitas CA) Reddy Srinivas T. (Santa Clara CA) Raman Rina (Fremont CA) Cope L. Todd (San Jose CA) Huang Joseph (San Jose CA) Pedersen Bruce B. (San Jose CA). Programmable logic array integrated circuit devices. USP1997115689195.
  11. Jefferson David E. ; McClintock Cameron ; Schleicher James ; Lee Andy L. ; Mejia Manuel ; Pedersen Bruce B. ; Lane Christopher F. ; Cliff Richard G. ; Reddy Srinivas T.. Programmable logic device architecture with super-regions having logic regions and a memory region. USP2001046215326.
  12. Lane Christopher F. ; Reddy Srinivas T. ; Cliff Richard G. ; Zaveri Ketan H. ; Pedersen Bruce B. ; Veenstra Kerry. Programmable logic device circuitry for improving multiplier speed and/or efficiency. USP2000056069487.
  13. Patel Rakesh H. (Santa Clara CA) Turner John E. (Santa Cruz CA) Wong Myron W. (San Jose CA). Programmable logic device having multiplexers and demultiplexers randomly connected to global conductors for interconnec. USP1994125371422.
  14. Wong Sau-Ching (Hillsborough CA) So Hock-Chuen (Milpitas CA) Kopec ; Jr. Stanley J. (San Jose CA) Hartmann Robert F. (San Jose CA). Programmable logic device with array blocks connected via programmable interconnect. USP1989104871930.
  15. Costello John C. (San Jose CA) Patel Rakesh H. (Santa Clara CA). Programmable logic device with logic block outputs coupled to adjacent logic block output multiplexers. USP1996015483178.

이 특허를 인용한 특허 피인용횟수: 227

  1. Ramchandran, Amit. Adaptable datapath for a digital processing system. USP2013028380884.
  2. Ramchandran, Amit. Adaptable datapath for a digital processing system. USP2015049015352.
  3. Ramchandran, Amit. Adaptable datapath for a digital processing system. USP2014048706916.
  4. Ramchandran, Amit. Adaptable datapath for a digital processing system. USP2009107606943.
  5. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter J.. Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements. USP2015109164952.
  6. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter J.. Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements. USP2013098543795.
  7. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James. Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements. USP2013098533431.
  8. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James. Adaptive integrated circuitry with heterogenous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements. USP2013098543794.
  9. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James. Adaptive processor for performing an operation with simple and complex units each comprising configurably interconnected heterogeneous elements. USP2013018356161.
  10. Langhammer, Martin; Nguyen, Triet M.; Lin, Yi-Wen. Adder-rounder circuitry for specialized processing block in programmable logic device. USP2010107822799.
  11. Langhammer, Martin. Angular range reduction in an integrated circuit device. USP2013078484265.
  12. Master, Paul L.; Uvacek, Bohumir. Apparatus and method for adaptive multimedia reception and transmission in communication environments. USP2015049002998.
  13. Master, Paul L.; Smith, Stephen J.; Watson, John. Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements. USP2016059330058.
  14. Master, Paul L.; Smith, Stephen J.; Watson, John. Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements. USP2014118880849.
  15. Master, Paul L.; Smith, Stephen J.; Watson, John. Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements. USP2012088250339.
  16. Master, Paul L.; Smith, Stephen J.; Watson, John. Apparatus, system and method for configuration of adaptive integrated circuitry having fixed, application specific computational elements. USP2017039594723.
  17. Master, Paul L.; Smith, Stephen J.; Watson, John. Apparatus, system and method for configuration of adaptive integrated circuitry having heterogeneous computational elements. USP2013048412915.
  18. Master, Paul L.; Smith, Stephen J.; Watson, John. Apparatus, system and method for configuration of adaptive integrated circuitry having heterogeneous computational elements. USP2012078225073.
  19. Simkins, James M.; Young, Steven P.; Wong, Jennifer; New, Bernard J.; Ching, Alvin Y.. Applications of cascading DSP slices. USP2009077567997.
  20. Ching, Alvin Y.; Wong, Jennifer; New, Bernard J.; Simkins, James M.; Thendean, John M.; Wong, Anna Wing Wah; Vadi, Vasisht Mantra. Architectural floorplan for a digital signal processing circuit. USP2010127853632.
  21. Simkins,James M.; Young,Steven P.; Wong,Jennifer; New,Bernard J.; Ching,Alvin Y.. Arithmetic circuit with multiplexed addend inputs. USP2009017480690.
  22. Wong, Anna Wing Wah; Wong, Jennifer; New, Bernard J.; Ching, Alvin Y.; Thendean, John M.; Simkins, James M.; Vadi, Vasisht Mantra; Schultz, David P.. Arithmetic logic unit circuit. USP2010117840630.
  23. Howard, Ric; Katragadda, Ramana V.. Asynchronous, independent and multiple process shared memory system in an adaptive computing architecture. USP2009087577799.
  24. Langhammer, Martin. Calculation of trigonometric functions in an integrated circuit device. USP2014088812573.
  25. Langhammer, Martin. Calculation of trigonometric functions in an integrated circuit device. USP2014108862650.
  26. Langhammer, Martin. Calculation of trigonometric functions in an integrated circuit device. USP2013088510354.
  27. Langhammer, Martin. Calculation of trigonometric functions in an integrated circuit device. USP2013118589463.
  28. Vorbach, Martin. Chip including memory element storing higher level memory data on a page by page basis. USP2016099436631.
  29. Vorbach, Martin; Münch, Robert. Circuit having a multidimensional structure of configurable cells that include multi-bit-wide inputs and outputs. USP2010107822968.
  30. Langhammer,Martin; Prasad,Nitin. Circuitry for arithmetically accumulating a succession of arithmetic values. USP2006047024446.
  31. Young,Steven P.. Columnar architecture. USP2007037187200.
  32. Young, Steven P.. Columnar floorplan. USP2009077557610.
  33. Young,Steven P.. Columnar floorplan. USP2006117132851.
  34. Langhammer, Martin. Combined adder and pre-adder for high-radix multiplier circuit. USP2017069684488.
  35. Langhammer, Martin. Combined floating point adder and subtractor. USP2014028645449.
  36. Mauer, Volker. Combined interpolation and decimation filter for programmable logic device. USP2010107814137.
  37. Heidari, Ghobad; Chang, Kuor Hsin; Master, Paul L.; Hogenauer, Eugene B.; Scheuermann, Walter James. Communications module, device, and method for implementing a system acquisition function. USP2009117620097.
  38. Jennings, Earle; Landers, George. Computer for Amdahl-compliant algorithms like matrix inversion. USP2014118892620.
  39. Langhammer, Martin. Computing floating-point polynomials in an integrated circuit device. USP2015028949298.
  40. Langhammer, Martin; Pasca, Bogdan. Computing floating-point polynomials in an integrated circuit device. USP2015069053045.
  41. Master, Paul L.; Watson, John. Configurable hardware based digital imaging apparatus. USP2009107609297.
  42. Vorbach, Martin; Nuckel, Armin. Configurable logic integrated circuit having a multidimensional structure of configurable elements. USP2017069690747.
  43. Vorbach, Martin; Nückel, Armin. Configurable logic integrated circuit having a multidimensional structure of configurable elements. USP2014058726250.
  44. Vezier, Loic; Tahiri, Farid. Configurable multiply-accumulate. USP2016079391621.
  45. Langhammer, Martin. Configuring a programmable integrated circuit device to perform matrix multiplication. USP2014018626815.
  46. Langhammer, Martin. Configuring floating point operations in a programmable device. USP2014028650231.
  47. Langhammer, Martin. Configuring floating point operations in a programmable logic device. USP2011017865541.
  48. Manohararajah, Valavan; Lewis, David. Configuring programmable integrated circuit device resources as processing elements. USP2017019553590.
  49. Scheuermann, W. James; Hogenauer, Eugene B.. Control node for multi-core system. USP20190110185502.
  50. Dante, Conrad. Converting bits to vectors in a programmable logic device. USP2005016844757.
  51. Leung, Wai-Bor; Lui, Henry Y.. DSP block for implementing large multiplier on a programmable integrated circuit device. USP2012118307023.
  52. Sihlbom, Bjorn; Stollon, Neal S.; McCaughey, Thomas. DSP integrated with programmable logic based accelerators. USP2003126667636.
  53. Langhammer, Martin. DSP processor architecture with write datapath word conditioning and analysis. USP2009097587438.
  54. Starr, Gregory; Langhammer, Martin; Hwang, Chiao Kai. Data latch with low-power bypass mode. USP2005106958624.
  55. Vorbach, Martin; Thomas, Alexander. Data processing device and method. USP2014088812820.
  56. Vorbach, Martin; Thomas, Alexander. Data processing device and method. USP2012038145881.
  57. Vorbach, Martin; Thomas, Alexander. Data processing device and method. USP2010117844796.
  58. Vorbach, Martin; Becker, Jürgen; Weinhardt, Markus; Baumgarte, Volker; May, Frank. Data processing method and device. USP2014128914590.
  59. Vorbach, Martin; Becker, Jürgen; Weinhardt, Markus; Baumgarte, Volker; May, Frank. Data processing method and device. USP2012048156284.
  60. Vorbach, Martin; Becker, Jürgen; Weinhardt, Markus; Baumgarte, Volker; May, Frank. Data processing system having integrated pipelined array data processor. USP2015109170812.
  61. Vorbach, Martin; May, Frank; Reichardt, Dirk; Lier, Frank; Ehlers, Gerd; Nückel, Armin; Baumgarte, Volker; Rao, Prashant; Oertel, Jens. Data processor chip with flexible bus system. USP2016029256575.
  62. Vorbach, Martin; Münch, Robert. Data processor having disabled cores. USP2014088819505.
  63. Hutton,Michael; Kaptanoglu,Sinan. Dedicated crossbar and barrel shifter block on programmable logic resources. USP2008047355442.
  64. Hutton,Michael; Kaptanoglu,Sinan. Dedicated crossbar and barrel shifter block on programmable logic resources. USP2006057042248.
  65. Hutton,Michael D.; Pedersen,Bruce B.; Schleicher, II,James G.. Dedicated resource interconnects. USP2008057368942.
  66. Vorbach, Martin. Device including a field having function cells and information providing cells controlled by the function cells. USP2013048429385.
  67. Langhammer, Martin; Starr, Gregory; Hwang, Chiao Kai. Devices and methods with programmable logic and digital signal processing regions. USP2004086771094.
  68. Vadi, Vasisht Mantra; Young, Steven P.; Ghia, Atul V.; Bekele, Adebabay M.; Menon, Suresh M.. Differential clock tree in an integrated circuit. USP2009047518401.
  69. New, Bernard J.; Vadi, Vasisht Mantra; Wong, Jennifer; Ching, Alvin Y.; Thendean, John M.; Wong, Anna Wing Wah; Simkins, James M.. Digital signal processing block having a wide multiplexer. USP2011017865542.
  70. Simkins, James M.; Ching, Alvin Y.; Thendean, John M.; Vadi, Vasisht M.; Poon, Chi Fung; Rab, Muhammad Asim. Digital signal processing block with preadder stage. USP2013098543635.
  71. Demirsoy, Suleyman Sirri; Yi, Hyun. Digital signal processing circuit blocks with support for systolic finite-impulse-response digital filtering. USP2013068458243.
  72. Demirsoy, Suleyman Sirri; Yi, Hyun. Digital signal processing circuit blocks with support for systolic finite-impulse-response digital filtering. USP2013118589465.
  73. Demirsoy, Suleyman; Yi, Hyun. Digital signal processing circuit blocks with support for systolic finite-impulse-response digital filtering. USP2014058732225.
  74. Simkins, James M.; Wong, Jennifer; New, Bernard J.; Ching, Alvin Y.; Thendean, John M.; Wong, Anna Wing Wah; Vadi, Vasisht Mantra. Digital signal processing circuit having a SIMD circuit. USP2010127853634.
  75. Vadi, Vasisht Mantra; Wong, Jennifer; New, Bernard J.; Ching, Alvin Y.; Thendean, John M.; Wong, Anna Wing Wah; Simkins, James M.. Digital signal processing circuit having a pattern circuit for determining termination conditions. USP2010127860915.
  76. Vadi, Vasisht Mantra; Wong, Jennifer; New, Bernard J.; Ching, Alvin Y.; Thendean, John M.; Wong, Anna Wing Wah; Simkins, James M.. Digital signal processing circuit having a pattern detector circuit. USP2010127849119.
  77. New, Bernard J.; Wong, Jennifer; Simkins, James M.; Ching, Alvin Y.; Thendean, John M.; Wong, Anna Wing Wah; Vadi, Vasisht Mantra. Digital signal processing circuit having a pattern detector circuit for convergent rounding. USP2010127853636.
  78. Simkins, James M.; Thendean, John M.; Vadi, Vasisht Mantra; New, Bernard J.; Wong, Jennifer; Wong, Anna Wing Wah; Ching, Alvin Y.. Digital signal processing circuit having a pre-adder circuit. USP2010117844653.
  79. Thendean, John M.; Wong, Jennifer; New, Bernard J.; Ching, Alvin Y.; Simkins, James M.; Wong, Anna Wing Wah; Vadi, Vasisht Mantra. Digital signal processing circuit having an adder circuit with carry-outs. USP2011017870182.
  80. Simkins, James M.; Wong, Jennifer; New, Bernard J.; Ching, Alvin Y.; Thendean, John M.; Wong, Anna Wing Wah; Vadi, Vasisht Mantra. Digital signal processing circuit having input register blocks. USP2010117840627.
  81. Langhammer, Martin. Digital signal processing circuitry with redundancy and ability to support larger multipliers. USP2014118886696.
  82. Langhammer, Martin; Lin, Yi-Wen; Streicher, Keone. Digital signal processing circuitry with redundancy and bidirectional data paths. USP2014088805916.
  83. Simkins, James M.; Wong, Jennifer; New, Bernard J.; Ching, Alvin Y.; Thendean, John M.; Wong, Anna Wing Wah; Vadi, Vasisht Mantra; Schultz, David P.. Digital signal processing element having an arithmetic logic unit. USP2011027882165.
  84. Langhammer, Martin. Discrete Fourier Transform in an integrated circuit device. USP2013128601044.
  85. Langhammer, Martin. Double-clocked specialized processing block in an integrated circuit device. USP2014028645451.
  86. Furtek, Frederick Curtis; Master, Paul L.. External memory controller. USP2012098266388.
  87. Furtek, Frederick Curtis; Master, Paul L.. External memory controller node. USP2014078769214.
  88. Furtek, Fredrick Curtis; Master, Paul L.. External memory controller node. USP2011077984247.
  89. Furtek, Fredrick Curtis; Master, Paul L.. External memory controller node. USP2011077979646.
  90. Minz, Deboleena; Digari, Kailash. Field programmable gate array. USP2012028112466.
  91. Langhammer, Martin. Fixed-point and floating-point arithmetic operator circuits in specialized processing blocks. USP20180810042606.
  92. Zheng, Leon; Langhammer, Martin; Prasad, Nitin; Starr, Greg; Hwang, Chiao Kai; Tharmalingam, Kumara. Flexible accumulator in digital signal processing circuitry. USP2010027660841.
  93. Zheng, Leon; Langhammer, Martin; Prasad, Nitin; Starr, Greg; Hwang, Chiao Kai; Tharmalingam, Kumara. Flexible accumulator in digital signal processing circuitry. USP2015109170775.
  94. Bauer,Trevor J.; Young,Steven P.. Formation of columnar application specific circuitry using a columnar programmable logic device. USP2009017478359.
  95. Vorbach, Martin; May, Frank. Hardware definition method including determining whether to implement a function as hardware or software. USP2012088250503.
  96. Scheuermann,Walter James. Hardware implementation of the secure hash standard. USP2009027489779.
  97. Scheuermann, W. James; Hogenauer, Eugene B.. Hardware task manager. USP2017059665397.
  98. Scheuermann, W. James; Hogenauer, Eugene B.. Hardware task manager. USP2012068200799.
  99. Scheuermann, W. James; Hogenauer, Eugene B.. Hardware task manager. USP2010017653710.
  100. Scheuermann, W. James; Hogenauer, Eugene B.. Hardware task manager. USP2014078782196.
  101. Sihlbom, Bjorn; Stollon, Neal S.; McCaughey, Thomas. Heterogeneous integrated circuit with reconfigurable logic cores. USP2003116653859.
  102. Master,Paul L.; Hogenauer,Eugene; Scheuermann,Walter James. Hierarchical interconnect for configuring separate interconnects for each group of fixed and diverse computational elements. USP2008017325123.
  103. Chou, Shin-I. High-rate interpolation or decimation filter in integrated circuit device. USP2014028650236.
  104. Vorbach, Martin; Münch, Robert. I/O and memory bus system for DFPS and units with two- or multi-dimensional programmable cell architectures. USP2012068195856.
  105. Burney,Ali H; Schlacter,Guy R. Implementing crossbars and barrel shifters using multiplier-accumulator blocks. USP2008037343388.
  106. Langhammer, Martin. Implementing division in a programmable integrated circuit device. USP2012088255448.
  107. Langhammer, Martin. Implementing large multipliers in a programmable integrated circuit device. USP2015028959137.
  108. Langhammer, Martin. Implementing mixed-precision floating-point operations in a programmable integrated circuit device. USP2014048706790.
  109. Langhammer, Martin. Implementing multipliers in a programmable integrated circuit device. USP2013068468192.
  110. Heidari-Bateni, Ghobad; Sambhwani, Sharad D.. Internal synchronization control for adaptive integrated circuitry. USP2012108296764.
  111. Langhammer, Martin; Tharmalingam, Kumara. Large multiplier for programmable logic device. USP2016079395953.
  112. Langhammer, Martin; Tharmalingam, Kumara. Large multiplier for programmable logic device. USP2014078788562.
  113. Langhammer, Martin; Tharmalingam, Kumara. Large multiplier for programmable logic device. USP2013028386553.
  114. Langhammer, Martin; Tharmalingam, Kumara. Large multiplier for programmable logic device. USP2015069063870.
  115. Vorbach, Martin; May, Frank; Reichardt, Dirk; Lier, Frank; Ehlers, Gerd; Nückel, Armin; Baumgarte, Volker; Rao, Prashant; Oertel, Jens. Logic cell array and bus system. USP2013068471593.
  116. Vorbach, Martin; May, Frank; Reichardt, Dirk; Lier, Frank; Ehlers, Gerd; Nückel, Armin; Baumgarte, Volker; Rao, Prashant; Oertel, Jens. Logic cell array and bus system. USP2011118058899.
  117. Vorbach, Martin; May, Frank; Reichardt, Dirk; Lier, Frank; Ehlers, Gerd; Nückel, Armin; Baumgarte, Volker; Rao, Prashant; Oertel, Jens. Logical cell array and bus system. USP2015069047440.
  118. Sambhwani, Sharad; Heidari, Ghobad. Low I/O bandwidth method and system for implementing detection and identification of scrambling codes. USP2013058442096.
  119. Sambhwani, Sharad; Heidari, Ghobad. Low I/O bandwidth method and system for implementing detection and identification of scrambling codes. USP2010027668229.
  120. Sambhwani,Sharad; Heidari,Ghobad. Low I/O bandwidth method and system for implementing detection and identification of scrambling codes. USP2009037512173.
  121. Langhammer, Martin. Matrix decomposition in an integrated circuit device. USP2013038396914.
  122. Kurtz, Brian L.. Matrix operations in an integrated circuit device. USP2014068762443.
  123. Langhammer, Martin. Matrix operations in an integrated circuit device. USP2013118577951.
  124. Vorbach, Martin; May, Frank; Nuckel, Armin. Method and device for processing data. USP2012108281265.
  125. Master, Paul L.. Method and system for achieving individualized protected space in an operating system. USP2010027660984.
  126. Master, Paul L.. Method and system for creating and programming an adaptive computing engine. USP2011017865847.
  127. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L.. Method and system for managing hardware resources to implement system functions using an adaptive computing architecture. USP2015059037834.
  128. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L.. Method and system for managing hardware resources to implement system functions using an adaptive computing architecture. USP2016079396161.
  129. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L.. Method and system for managing hardware resources to implement system functions using an adaptive computing architecture. USP2013118589660.
  130. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L.. Method and system for managing hardware resources to implement system functions using an adaptive computing architecture. USP2010077752419.
  131. Scheuermann, W. James. Method and system for reconfigurable channel coding. USP2014078767804.
  132. Scheuermann, W. James. Method and system for reconfigurable channel coding. USP2012088249135.
  133. Scheuermann, W. James. Method and system for reconfigurable channel coding. USP2010107809050.
  134. Scheuermann, W. James. Method and system for reconfigurable channel coding. USP2010107822109.
  135. Mauer, Volker; Demirsoy, Suleyman Sirri. Method for configuring a finite impulse response filter in a programmable logic device. USP2013028386550.
  136. Vorbach, Martin. Method for debugging reconfigurable architectures. USP2013038407525.
  137. Vorbach, Martin. Method for debugging reconfigurable architectures. USP2011118069373.
  138. Vorbach, Martin; May, Frank; Nückel, Armin. Method for debugging reconfigurable architectures. USP2010117840842.
  139. Vorbach, Martin; Nückel, Armin. Method for interleaving a program over a plurality of cells. USP2012078230411.
  140. Vorbach, Martin; May, Frank; Weinhardt, Markus; Cardoso, Joao Manuel Paiva. Method for processing data. USP20180710031733.
  141. Vorbach, Martin; Nückel, Armin; May, Frank; Weinhardt, Markus; Cardoso, Joao Manuel Paiva. Method for processing data. USP2010027657877.
  142. Tharmalingam,Kumara. Method for programming programmable logic device having specialized functional blocks. USP2006077082592.
  143. Bansal, Jai P.. Method for providing a cell-based ASIC device with multiple power supply voltages. USP2005096944843.
  144. Vorbach, Martin; May, Frank; Nückel, Armin. Method for the translation of programs for reconfigurable architectures. USP2014108869121.
  145. Wendling, Xavier; Simkins, James M.. Method of and circuit for implementing a filter in an integrated circuit. USP2013078479133.
  146. Haight,Charles Francis. Method of implementing a high-speed header bypass function. USP2007127310728.
  147. Wicker, Jr., David J.. Method of optimizing routing in a programmable logic device. USP2004106809551.
  148. Vorbach, Martin; Baumgarte, Volker; May, Frank; Nuckel, Armin. Method of processing data with an array of data processors according to application ID. USP2015099141390.
  149. Dante, Conrad. Method of routing in a programmable logic device. USP2005066907592.
  150. Vorbach, Martin; Munch, Robert M.. Method of self-synchronization of configurable elements of a programmable module. USP201409RE45109.
  151. Vorbach, Martin; Münch, Robert M.. Method of self-synchronization of configurable elements of a programmable module. USP201410RE45223.
  152. Vorbach, Martin; Münch, Robert M.. Method of self-synchronization of configurable elements of a programmable module. USP201307RE44383.
  153. Vorbach, Martin; Münch, Robert M.. Method of self-synchronization of configurable elements of a programmable module. USP201307RE44365.
  154. Master,Paul L.; Hogenauer,Eugene; Wu,Bicheng William; Chuang,Dan MingLun; Freeman Benson,Bjorn. Method, system and program for developing and scheduling adaptive integrated circuity and corresponding control or configuration information. USP2009017478031.
  155. Vorbach, Martin; Baumgarte, Volker. Methods and devices for treating and processing data. USP2015079075605.
  156. Vorbach, Martin; Baumgarte, Volker. Methods and devices for treating and processing data. USP2012018099618.
  157. Vorbach, Martin; Baumgarte, Volker. Methods and devices for treating and processing data. USP2012118312301.
  158. Vorbach, Martin; Baumgarte, Volker; May, Frank; Nuckel, Armin. Methods and systems for transferring data between a processing device and external devices. USP2016089411532.
  159. Langhammer, Martin. Methods for specifying processor architectures for programmable integrated circuits. USP20181010110233.
  160. Langhammer, Martin; Lee, Kwan Yee Martin; Burney, Ali H.. Mixed-mode multiplier using hard and soft logic circuitry. USP2014108856201.
  161. Streicher, Keone; Langhammer, Martin; Lin, Yi-Wen; Leung, Wai-Bor; Lewis, David; Mauer, Volker; Lui, Henry Y.; Demirsoy, Suleyman Sirri; Yi, Hyun. Modular digital signal processing circuitry with optionally usable, dedicated connections between modules of the circuitry. USP2014068751551.
  162. Streicher, Keone; Langhammer, Martin; Lin, Yi-Wen; Leung, Wai-Bor; Lewis, David; Mauer, Volker; Lui, Henry Y.; Demirsoy, Suleyman Sirri; Yi, Hyun. Modular digital signal processing circuitry with optionally usable, dedicated connections between modules of the circuitry. USP2013108549055.
  163. Streicher, Keone; Langhammer, Martin; Lin, Yi-Wen; Leung, Wai-Bor; Lewis, David; Mauer, Volker; Lui, Henry Y.; Demirsoy, Suleyman Sirri; Yi, Hyun. Modular digital signal processing circuitry with optionally usable, dedicated connections between modules of the circuitry. USP2013128620977.
  164. Langhammer,Martin. Multi-functional digital signal processing circuitry. USP2007107287051.
  165. Langhammer, Martin. Multi-operand floating point operations in a programmable integrated circuit device. USP2013048412756.
  166. Vorbach, Martin; Baumgarte, Volker; May, Frank; Nuckel, Armin. Multi-processor bus and cache interconnection system. USP2016029250908.
  167. Vorbach, Martin. Multi-processor with selectively interconnected memory units. USP2016039274984.
  168. Langhammer, Martin. Multiple-precision processing block in a programmable integrated circuit device. USP2015119189200.
  169. Zheng,Leon; Langhammer,Martin; Perry,Steven; Metzgen,Paul; Starr,Gregory; Hwang,William; Tharmalingam,Kumara. Multiplier-accumulator block mode splitting. USP2008107437401.
  170. Choe, Kok Heng; Ngai, Tony K; Lui, Henry Y.. Multiplier-accumulator circuitry and methods. USP2014028645450.
  171. Vorbach, Martin; Baumgarte, Volker. Multiprocessor having runtime adjustable clock and clock dependent power supply. USP2017019552047.
  172. Langhammer, Martin. Normalization of floating point operations in a programmable integrated circuit device. USP2012088244789.
  173. Langhammer, Martin. Normalization of floating point operations in a programmable integrated circuit device. USP2014118886695.
  174. Vorbach, Martin; Baumgarte, Volker; Ehlers, Gerd; May, Frank; Nückel, Armin. Pipeline configuration protocol and configuration unit communication. USP2012108301872.
  175. Vorbach, Martin; Baumgarte, Volker; Ehlers, Gerd; May, Frank; Nückel, Armin. Pipeline configuration protocol and configuration unit communication. USP2013068468329.
  176. Mauer, Volker; Langhammer, Martin. Pipelined systolic finite impulse response filter. USP2016069379687.
  177. Langhammer, Martin. Polynomial calculations optimized for programmable integrated circuit device structures. USP2015129207909.
  178. Vorbach, Martin; Münch, Robert. Process for automatic dynamic reloading of data flow processors (DFPs) and units with two- or three-dimensional programmable cell architectures (FPGAs, DPGAs, and the like). USP2010107822881.
  179. Vorbach, Martin. Processor arrangement on a chip including data processing, memory, and interface elements. USP2015059037807.
  180. Vorbach, Martin; Münch, Robert. Processor chip for reconfigurable data processing, for processing numeric and logic operations and including function and interconnection control units. USP2012048156312.
  181. Vorbach, Martin; Nückel, Armin. Processor chip including a plurality of cache elements connected to a plurality of processor cores. USP2012118312200.
  182. Master, Paul L.. Profiling of software and circuit designs utilizing data operation analyses. USP2012098276135.
  183. Langhammer, Martin. Programmable device using fixed and configurable logic to implement floating-point rounding. USP2016059348795.
  184. Langhammer, Martin. Programmable device using fixed and configurable logic to implement recursive trees. USP2017039600278.
  185. Simkins, James M.; Young, Steven P.; Wong, Jennifer; New, Bernard J.; Ching, Alvin Y.. Programmable device with dynamic DSP architecture. USP2013078495122.
  186. Mauer, Volker; Langhammer, Martin. Programmable device with specialized multiplier blocks. USP2013128620980.
  187. Hazanchuk, Asher. Programmable logic device data rate booster for digital signal processing. USP2015038977885.
  188. Lewis,David; Cashman,David. Programmable logic device having logic array block interconnect lines that can interconnect logic elements in different logic blocks. USP2008117456653.
  189. Lewis,David; Cashman,David. Programmable logic device having redundancy with logic element granularity. USP2009037508231.
  190. Langhammer,Martin; Hwang,Chiao Kai; Starr,Gregory. Programmable logic device including multipliers and configurations thereof to reduce resource utilization. USP2007057216139.
  191. Simkins,James M.; Young,Steven P.; Wong,Jennifer; New,Bernard J.; Ching,Alvin Y.. Programmable logic device with cascading DSP slices. USP2008127472155.
  192. Simkins,James M.; Young,Steven P.; Wong,Jennifer; New,Bernard J.; Ching,Alvin Y.. Programmable logic device with pipelined DSP slices. USP2008127467175.
  193. Langhammer, Martin. Programmable logic device with routing channels. USP2004086781408.
  194. Langhammer,Martin. Programmable logic device with routing channels. USP2007067230451.
  195. Langhammer,Martin. Programmable logic device with routing channels. USP2006117142011.
  196. Langhammer,Martin. Programmable logic device with routing channels. USP2006097109753.
  197. Langhammer, Martin; Zheng, Leon; Hwang, Chiao Kai; Starr, Gregory. Programmable logic device with specialized functional block. USP2010047698358.
  198. Langhammer, Martin; Zheng, Leon; Hwang, Chiao Kai; Starr, Gregory. Programmable logic device with specialized functional block. USP2013018364738.
  199. Langhammer, Martin. Programmable logic device with specialized multiplier blocks. USP2009097590676.
  200. Langhammer, Martin; Prasad, Nitin. Programmable logic devices with function-specific blocks. USP2011087991812.
  201. Langhammer, Martin. QR decomposition in an integrated circuit device. USP2013098539016.
  202. Mauer, Volker. QR decomposition in an integrated circuit device. USP2014088812576.
  203. Vorbach, Martin. Reconfigurable elements. USP2014048686475.
  204. Vorbach, Martin. Reconfigurable elements. USP2014048686549.
  205. Vorbach, Martin; Baumgarte, Volker. Reconfigurable general purpose processor having time restricted configurations. USP2012108281108.
  206. Vorbach, Martin. Reconfigurable sequencer structure. USP2014088803552.
  207. Vorbach, Martin. Reconfigurable sequencer structure. USP2012118310274.
  208. Vorbach, Martin. Reconfigurable sequencer structure. USP2010087782087.
  209. Vorbach, Martin; Bretz, Daniel. Router. USP2012068209653.
  210. Patil, Vishnu A.; Prasanth, Karyampoodi Bhanu; Shiao, Wilma W.; Pagarani, Tarachand; Chakrabarti, Pinaki. Routing network for programmable logic device. USP2015089118325.
  211. Zheng, Leon; Langhammer, Martin; Perry, Steven; Metzgen, Paul; Prasad, Nitin; Hwang, William. Saturation and rounding in multiply-accumulate blocks. USP2013128615543.
  212. Zheng,Leon; Langhammer,Martin; Perry,Steven; Metzgen,Paul; Prasad,Nitin; Hwang,William. Saturation and rounding in multiply-accumulate blocks. USP2008127467176.
  213. Langhammer, Martin; Dhanoa, Kulwinder. Solving linear matrices in an integrated circuit device. USP2013098539014.
  214. Langhammer, Martin. Specialized processing block for implementing floating-point multiplier with subnormal operation support. USP2015038996600.
  215. Xu, Lei; Mauer, Volker; Perry, Steven. Specialized processing block for programmable integrated circuit device. USP2013098543634.
  216. Langhammer, Martin; Lee, Kwan Yee Martin; Azgomi, Orang; Streicher, Keone; Lin, Yi-Wen. Specialized processing block for programmable logic device. USP2012098266199.
  217. Langhammer, Martin; Lee, Kwan Yee Martin; Azgomi, Orang; Streicher, Keone; Pelt, Robert L.. Specialized processing block for programmable logic device. USP2011108041759.
  218. Langhammer, Martin; Lee, Kwan Yee Martin; Nguyen, Triet M.; Streicher, Keone; Azgomi, Orang. Specialized processing block for programmable logic device. USP2010117836117.
  219. Lee, Kwan Yee Martin; Langhammer, Martin; Lin, Yi-Wen; Nguyen, Triet M.. Specialized processing block for programmable logic device. USP2012098266198.
  220. Lee, Kwan Yee Martin; Langhammer, Martin; Nguyen, Triet M.; Lin, Yi-Wen. Specialized processing block for programmable logic device. USP2012108301681.
  221. Langhammer, Martin. Specialized processing block with fixed- and floating-point structures. USP2015089098332.
  222. Hwang, Chiao Kai; Starr, Gregory; Langhammer, Martin. Specialized programmable logic region with low-power mode. USP2005086937062.
  223. Master,Paul L.; Watson,John. Storage and delivery of device features. USP2009027493375.
  224. Master, Paul L.; Watson, John. System for adapting device standards after manufacture. USP2009107602740.
  225. Master, Paul L.; Watson, John. System for authorizing functionality in adaptable hardware devices. USP201109E042743.
  226. Katragadda, Ramana; Spoltore, Paul; Howard, Ric. Task definition for specifying resource requirements. USP2012018108656.
  227. Dante, Conrad; Rutledge, David Lee; Wicker, Jr., David J.. Vector routing in a programmable logic device. USP2004116812738.