초록 ▼

A programmable logic integrated circuit device ("PLD") includes programmable logic and a dedicated (i.e., at least partly hard-wired) digital signal processing region for performing or at least helping to perform digital signal processing tasks that are unduly inefficient to implement in the more ge

A programmable logic integrated circuit device ("PLD") includes programmable logic and a dedicated (i.e., at least partly hard-wired) digital signal processing region for performing or at least helping to perform digital signal processing tasks that are unduly inefficient to implement in the more general-purpose programmable logic and/or that, if implemented in the programmable logic, would operate unacceptably or at least undesirably slowly. The digital signal processing region may include multiple digital signal processing stages. The digital signal processing region may include a multiplier stage and one ore more stages that can operate in combination with the multiplier stage. The digital signal processing region has a plurality of modes such as for providing multiply-and-accumulate operation, multiply-and-add operation, etc.

대표청구항 ▼

A programmable logic integrated circuit device ("PLD") includes programmable logic and a dedicated (i.e., at least partly hard-wired) digital signal processing region for performing or at least helping to perform digital signal processing tasks that are unduly inefficient to implement in the more ge

A programmable logic integrated circuit device ("PLD") includes programmable logic and a dedicated (i.e., at least partly hard-wired) digital signal processing region for performing or at least helping to perform digital signal processing tasks that are unduly inefficient to implement in the more general-purpose programmable logic and/or that, if implemented in the programmable logic, would operate unacceptably or at least undesirably slowly. The digital signal processing region may include multiple digital signal processing stages. The digital signal processing region may include a multiplier stage and one ore more stages that can operate in combination with the multiplier stage. The digital signal processing region has a plurality of modes such as for providing multiply-and-accumulate operation, multiply-and-add operation, etc. e variation between the probe (2) and the pair of detecting electrodes (3, 4). claim 27, wherein said two permanent magnets between which said coil of said electromagnet attached to said rotary system is movable are magnetized to opposite poles. 38. A thickness-measuring device as defined by claim 28, wherein said two permanent magnets between which said coil of said electromagnet attached to said rotary system is movable are magnetized to opposite poles. 39. A thickness-measuring device as defined by claim 29, wherein said two permanent magnets between which said coil of said electromagnet attached to said rotary system is movable are magnetized to opposite poles. 40. A thickness-measuring device as defined by claim 3, wherein said electronic system comprises: means for generating an electrical current which increases from zero and progresses linearly toward infinity for energizing said coil of said electromagnet; means for detecting an irregularit