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An RF transponder identification system with an interrogator operable to transmit a plurality of marker signals and a plurality of transponder. Each transponder has a random number associated therewith, a counter counting the number of marker signals received from the interrogator and transmission m

An RF transponder identification system with an interrogator operable to transmit a plurality of marker signals and a plurality of transponder. Each transponder has a random number associated therewith, a counter counting the number of marker signals received from the interrogator and transmission means to transmit an identification code when the number of marker signals received by the transponder equals the random number associated with the transponder.

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An RF transponder identification system with an interrogator operable to transmit a plurality of marker signals and a plurality of transponder. Each transponder has a random number associated therewith, a counter counting the number of marker signals received from the interrogator and transmission m

An RF transponder identification system with an interrogator operable to transmit a plurality of marker signals and a plurality of transponder. Each transponder has a random number associated therewith, a counter counting the number of marker signals received from the interrogator and transmission means to transmit an identification code when the number of marker signals received by the transponder equals the random number associated with the transponder. receiving one or more of the multiplier outputs and comprising circuitry that applies a particular digital signal processing operation to the received multiplier outputs; and interconnect resources that interconnect the digital signal processing region to at least some of the programmable logic regions. 2. The programmable logic device of claim 1 wherein the digital signal processing region has a plurality of different configurable modes of operation. 3. The programmable logic device of claim 2 wherein the digital signal processing region has a first plurality of modes in which the multiplier circuits implement n×n bit multiplications and a second plurality of modes in which the multiplier circuits implement n/2×n/2 bit multiplications. 4. The programmable logic device of claim 2 wherein the digital signal processing region has a plurality of modes in which the multiplier circuits implement n×n bit multiplications and an another mode in which the multiplier circuits implement 2n×2n bit multiplications. 5. The programable logic device of claim 1 wherein the digital signal process circuit is arranged to be dedicated to perform an addition operation. 6. The programmable logic device of claim 1 wherein the digital signal processing circuit is a first digital signal processing circuit that has a first digital signal processing circuit output and the programmable logic device further comprising a second digital signal processing circuit receiving the first digital signal processing circuit output, and comprising circuitry arranged to be dedicated to perform a specific digital signal processing operation. 7. The programmable logic device of claim 1 wherein the digital signal processing region is located in close proximity to the multiplier circuits. 8. The programmable logic device of claim 1 wherein the one or more multiplier outputs are received by the digital signal processing circuit without the one or more multiplier outputs being routed out of digital signal processing region. 9. The programmable logic device of claim 1 wherein the digital signal processing region covers an area in the programmable logic device that is substantially block-shaped. 10. The programmable logic device of claim 1 wherein the digital signal processing region further comprises pipeline register circuits that feed one or more multiplier outputs to the digital signal processing circuit. 11. The programmable logic device of claim 10 wherein the pipeline register circuits comprises a plurality of registers and a plurality of bypass circuits that selectively bypass the registers. 12. The programmable logic device of claim 1 wherein the digital signal processing region further comprises input register circuits that feed the plurality of multiplier circuits. 13. The programmable logic device of claim 12 wherein the input register circuits comprises a plurality of registers and a plurality of bypass circuits that selectively bypass the registers. 14. The programmable logic device of claim 1 wherein the digital signal processing region has a region output that is at least partly based on the multiplier outputs and wherein the digital signal processing region further comprises output register circuits that feed the region output to the interconnect resources. 15. The programmable logic device of claim 14 wherein the output register circuits comprises a plurality of registers and a plurality of bypass circuits that selectively bypass the registers. 16. The programmable logic device of claim 1 wherein the circuitry of digital signal processing circuit is arranged to be dedicated to perform that particular digital signal processing operation. 17. The programmable logic device of claim 1 wherein the circuitry of digital signal processing circuit is arranged to be dedicated to perform an addition or a subtraction operation. 18. The programmable logic device of claim 1 wherein each of the multiplier circuits comprises circuitry that is arranged to be dedicated