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An integrated circuit device includes a clock generator having a primary input for coupling to a primary reference frequency source, a secondary input for coupling to a secondary reference frequency source, and an output that produces a primary digital transceiver clock signal having a frequency of

An integrated circuit device includes a clock generator having a primary input for coupling to a primary reference frequency source, a secondary input for coupling to a secondary reference frequency source, and an output that produces a primary digital transceiver clock signal having a frequency of chiprate (S)(n) in a primary mode, and a secondiary digital transceiver clock signal having a frequency of chiprate in a secondary power saving mode. A chiprate divider connected to the output of the clock generator produces a primary mode enable signal that has a frequency of chiprate when in a primary mode. A long PN generator and a short PN generator each have a clock input that is coupled to the output of the clock generator. A first multiplexer output produces the primary mode enable signal in a primary mode, and the secondary mode enable signal in a secondary mode. A clock calibrator measures the frequency difference between 1/(S)(n) times the frequency of the primary digital transceiver clock signal and the frequency of the secondary digital transceiver clock signal as a function of time. A secondary mode timer indicates the amount of time the secondary mode is in effect. A controller calculates the cumulative resluting frequency error, and produces a signal for advancing or retarding a master timer to reduce the frequency error between the long PN generator and the short PN generator on the one hand, and the CDMA network time on the other hand.

대표청구항 ▼

An integrated circuit device includes a clock generator having a primary input for coupling to a primary reference frequency source, a secondary input for coupling to a secondary reference frequency source, and an output that produces a primary digital transceiver clock signal having a frequency of

An integrated circuit device includes a clock generator having a primary input for coupling to a primary reference frequency source, a secondary input for coupling to a secondary reference frequency source, and an output that produces a primary digital transceiver clock signal having a frequency of chiprate (S)(n) in a primary mode, and a secondiary digital transceiver clock signal having a frequency of chiprate in a secondary power saving mode. A chiprate divider connected to the output of the clock generator produces a primary mode enable signal that has a frequency of chiprate when in a primary mode. A long PN generator and a short PN generator each have a clock input that is coupled to the output of the clock generator. A first multiplexer output produces the primary mode enable signal in a primary mode, and the secondary mode enable signal in a secondary mode. A clock calibrator measures the frequency difference between 1/(S)(n) times the frequency of the primary digital transceiver clock signal and the frequency of the secondary digital transceiver clock signal as a function of time. A secondary mode timer indicates the amount of time the secondary mode is in effect. A controller calculates the cumulative resluting frequency error, and produces a signal for advancing or retarding a master timer to reduce the frequency error between the long PN generator and the short PN generator on the one hand, and the CDMA network time on the other hand. omparator for controlling the light power of the laser in a fashion independent of the monitoring signal polarity. 3. Method according to claim 1, further comprising the step of producing, at the second comparator, a signal which initially feeds to the first comparator the inverted monitoring signal in a fashion always independent of the monitoring signal polarity, and then feeds it in a non-inverted fashion if the monitoring signal runs up to the first reference value. 4. Method according to claim 1, wherein the second reference value is smaller than the first reference value. 5. Circuit arrangement for a laser control loop, comprising: a photodetector providing a monitoring signal having a signal polarity; a second comparator coupled to the photodetector and responsive to said monitoring signal for detecting the monitoring signal polarity by comparing the monitoring signal with a second reference value, which is smaller than a first reference value, for controlling the light power of the laser during a starting phase of the laser control loop, when a supply voltage is applied to a driver of the laser; an inverter for inverting the polarity of the monitoring signal; and a first comparator for comparing the monitoring signal directly or via said inverter in response to the monitoring signal polarity detected by said second comparator with said first reference value, the light power of the laser being controlled in response to an output of the first comparator. 6. Circuit arrangement according to claim 5, wherein the second comparator is connected to a control input of a changeover switch at which the first comparator is connected at the photodetector or via an inverter at the photodetector. 7. Circuit arrangement according to claim 6, wherein the changeover switch is an electronic switch. 8. Circuit arrangement according to claim 5, wherein during the starting phase of the laser control loop the first comparator is always connected via an inverter to the monitor or is always connected directly to the monitor in a fashion corresponding to the polarity of the reference signal appled at the second comparator. 9. Circuit arrangement according to claim 5, wherein the second comparator is a difference amplifier. 10. Circuit arrangement according to claim 5, wherein the second comparator is a current mirror connected to a second reference current source. object-side surface thereof. 15. The electronic image pickup system according to claim 1 or 4, which comprises a zoom lens wherein said first lens group comprises, in order from an object side thereof, a negative lens group comprising up to 2 negative lenses and a positive lens group comprising one positive lens, at least one negative lens in said lens group comprises an aspherical surface, and the following condition (7) is satisfied: -0.1W/R1111is an axial radius of curvature of the first lens surface in the first lens group, as counted from the object side, and fW is a focal length of the zoom lens system at a wide-angle end thereof upon focused on an object point at infinity. 16. The electronic image pickup system according to claim 1 or 4, which comprises a zoom lens that satisfies the following condition (8): 0.13Np/fWNpis an axial air separation between the negative and positive lens groups in the first lens group. 17. The electronic image pickup system according to claim 4, which comprises a zoom lens wherein said first lens group consists of, in order from an object side thereof, one positive lens, two negative lenses and one positive lens. 18. The electronic image pickup system according to claim 17, which comprises a zoom lens that satisfies the following condition (9): 0.7514/L14is an axial radius of curvature of the fourth lens surface in the first lens group, as counted from the object side, and L is a diagonal length of an effective image pickup area of the image pickup device. 19. The electronic image pickup system according to claim 1 or 4, wherein said first lens group, and said second lens group has a total thickness that satisfies the following conditions (11) and (12): 0.41/L2/L1is an axial thickness of the first lens group from a lens surface located nearest to an object side thereof to an lens surface located nearest to an image side thereof, t2is an axial thickness of the second lens group from a lens surface located nearest to an object side thereof to a lens surface located nearest to an image side thereof, and L is a diagonal length of an effective image pickup area of the image pickup device. 20. The electronic image pickup system according to claim 1 or 4, wherein an optical low-pass filter located between said image pickup device and the object side of said electronic image pickup system has a total thickness that satisfies the following condition (13): 0.15×103LPF/a3