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Semiconductor device and method of manufacturing the same 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-029/76
  • H01L-029/94
  • H01L-031/062
  • H01L-031/113
  • H01L-031/119
출원번호 US-0726486 (2000-12-01)
우선권정보 JP-0345426 (1999-12-03); JP-0012107 (2000-01-20)
발명자 / 주소
  • Nishinohara, Kazumi
  • Akasaka, Yasushi
  • Suguro, Kyoichi
출원인 / 주소
  • Kabushiki Kaisha Toshiba
대리인 / 주소
    Finnegan, Henderson, Farabow, Garrett & Dunner, L.L.P.
인용정보 피인용 횟수 : 189  인용 특허 : 6

초록 ▼

A semiconductor device has a first semiconductor region formed in a semiconductor substrate and having a first conductivity type due to first-conductivity-type active impurities contained in the first semiconductor region, and a second semiconductor region formed between the first semiconductor regi

대표청구항 ▼

A semiconductor device has a first semiconductor region formed in a semiconductor substrate and having a first conductivity type due to first-conductivity-type active impurities contained in the first semiconductor region, and a second semiconductor region formed between the first semiconductor regi

이 특허에 인용된 특허 (6)

  1. Bulucea Constantin ; Kerr Daniel C., Design and fabrication of semiconductor structure having complementary channel-junction insulated-gate field-effect tra.
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  2. Noguchi Tatsuo (Yokohama JPX), Field-effect transistor devices.
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  3. Aoki Kenji,JPX ; Takada Ryoji,JPX, MOS field effect transistor and its manufacturing method.
    상세보기
  4. Lee Yong-hee (Seoul KRX), Metal oxide semiconductor transistor and a method for manufacturing the same.
    상세보기
  5. Yamazaki Shunpei (Tokyo JPX), Method for the manufacture of an insulated gate field effect semiconductor device using photo enhanced CVD.
    상세보기
  6. Dennen Michael W. (Raleigh NC), Short channel fermi-threshold field effect transistors including drain field termination region and methods of fabricati.
    상세보기

이 특허를 인용한 특허 (189)

  1. Shifren, Lucian; Ranade, Pushkar; Gregory, Paul E.; Sonkusale, Sachin R.; Zhang, Weimin; Thompson, Scott E., Advanced transistors with punch through suppression.
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  2. Shifren, Lucian; Ranade, Pushkar; Gregory, Paul E.; Sonkusale, Sachin R.; Zhang, Weimin; Thompson, Scott E., Advanced transistors with punch through suppression.
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  3. Shifren, Lucian; Ranade, Pushkar; Gregory, Paul E.; Sonkusale, Sachin R.; Zhang, Weimin; Thompson, Scott E., Advanced transistors with punch through suppression.
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  4. Lee, Sang-Soo; Ahn, Heetae; Kuo, Augustine, Analog circuits having improved insulated gate transistors, and methods therefor.
    상세보기
  5. Clark, Lawerence T.; Thompson, Scott E., Analog circuits having improved transistors, and methods therefor.
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  6. Clark, Lawrence T.; Thompson, Scott E., Analog circuits having improved transistors, and methods therefor.
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  7. Clark, Lawrence T.; Thompson, Scott E., Analog circuits having improved transistors, and methods therefor.
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  8. Shifren, Lucian; Thompson, Scott E.; Gregory, Paul E., Analog transistor.
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  9. Ding, Yi, Arrays of nonvolatile memory cells wherein each cell has two conductive floating gates.
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  10. Clark, Lawrence T., Bit interleaved low voltage static random access memory (SRAM) and related methods.
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  11. Clark, Lawrence T.; McGregor, Michael S.; Rogenmoser, Robert; Kidd, David A.; Kuo, Augustine, Body bias circuits and methods.
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  12. Clark, Lawrence T.; McGregor, Michael S.; Rogenmoser, Robert; Kidd, David A.; Kuo, Augustine, Body bias circuits and methods.
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  13. Lindert, Nick; Cea, Stephen M., Bulk non-planar transistor having strained enhanced mobility and methods of fabrication.
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  14. Bakhishev, Teymur; Wang, Lingquan; Zhao, Dalong; Ranade, Pushkar; Thompson, Scott E., Buried channel deeply depleted channel transistor.
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  15. Bakhishev, Teymur; Wang, Lingquan; Zhao, Dalong; Ranade, Pushkar; Thompson, Scott E., Buried channel deeply depleted channel transistor.
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  16. Bakhishev, Teymur; Wang, Lingquan; Zhao, Dalong; Ranade, Pushkar; Thompson, Scott E., Buried channel deeply depleted channel transistor.
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  17. Doyle, Brian S.; Jin, Been-Yih; Kavalieros, Jack T.; Datta, Suman; Brask, Justin K.; Chau, Robert S., CMOS devices with a single work function gate electrode and method of fabrication.
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  18. Hoffmann, Thomas; Ranade, Pushkar; Thompson, Scott E., CMOS gate stack structures and processes.
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  19. Hoffmann, Thomas; Ranade, Pushkar; Thompson, Scott E., CMOS gate stack structures and processes.
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  20. Hoffmann, Thomas; Thompson, Scott E.; Ranade, Pushkar, CMOS gate stack structures and processes.
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  21. Thompson, Scott E.; Hoffmann, Thomas; Scudder, Lance; Sridharan, U. C.; Zhao, Dalong; Ranade, Pushkar; Duane, Michael; Gregory, Paul E., CMOS structures and processes based on selective thinning.
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  22. Thompson, Scott E.; Hoffmann, Thomas; Scudder, Lance; Sridharan, Urupattur C.; Zhao, Dalong; Ranade, Pushkar; Duane, Michael; Gregory, Paul, CMOS structures and processes based on selective thinning.
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  23. Clark, Lawrence T.; McWilliams, Bruce; Rogenmoser, Robert, Circuit devices and methods having adjustable transistor body bias.
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  24. Lee, Sang-Soo; Boling, Edward J.; Kuo, Augustine; Rogenmoser, Robert, Circuits and devices for generating bi-directional body bias voltages, and methods therefor.
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  25. Clark, Lawrence T.; Roy, Richard S., Circuits and methods for measuring circuit elements in an integrated circuit device.
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  26. Clark, Lawrence T; Roy, Richard S, Circuits and methods for measuring circuit elements in an integrated circuit device.
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  27. Hoffmann, Thomas; Shifren, Lucian; Thompson, Scott E.; Ranade, Pushkar; Wang, Jing; Gregory, Paul E.; Sonkusale, Sachin R.; Scudder, Lance; Zhao, Dalong; Bakhishev, Teymur; Liu, Yujie; Wang, Lingquan; Zhang, Weimin; Pradhan, Sameer; Duane, Michael; Kim, Sung Hwan, Deeply depleted MOS transistors having a screening layer and methods thereof.
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  28. Brask, Justin K.; Datta, Suman; Doczy, Mark L.; Blackwell, James M.; Metz, Matthew V.; Kavalieros, Jack T.; Chau, Robert S., Dielectric interface for group III-V semiconductor device.
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  29. Thompson, Scott E.; Clark, Lawrence T., Digital circuits having improved transistors, and methods therefor.
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  30. Thompson, Scott E.; Clark, Lawrence T., Digital circuits having improved transistors, and methods therefor.
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  31. Thompson, Scott E.; Clark, Lawrence T., Digital circuits having improved transistors, and methods therefor.
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  32. Thompson, Scott E.; Clark, Lawrence T., Digital circuits having improved transistors, and methods therefor.
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  33. Thompson, Scott E.; Clark, Lawrence T., Digital circuits having improved transistors, and methods therefor.
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  34. Thompson, Scott E.; Clark, Lawrence T., Digital circuits having improved transistors, and methods therefor.
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  35. Clark, Lawrence T.; Shifren, Lucian; Roy, Richard S., Dynamic random access memory (DRAM) with low variation transistor peripheral circuits.
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  36. Shifren, Lucian; Ranade, Pushkar, Electronic device with controlled threshold voltage.
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  37. Shifren, Lucian; Ranade, Pushkar, Electronic device with controlled threshold voltage.
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  38. Thompson, Scott E.; Thummalapally, Damodar R., Electronic devices and systems, and methods for making and using same.
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  39. Thompson, Scott E.; Thummalapally, Damodar R., Electronic devices and systems, and methods for making and using the same.
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  40. Thompson, Scott E.; Thummalapally, Damodar R., Electronic devices and systems, and methods for making and using the same.
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  41. Thompson, Scott E.; Thummalapally, Damodar R., Electronic devices and systems, and methods for making and using the same.
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  42. Thompson, Scott E.; Thummalapally, Damodar R., Electronic devices and systems, and methods for making and using the same.
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  43. Thompson, Scott E.; Thummalapally, Damodar R., Electronic devices and systems, and methods for making and using the same.
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  44. Thompson, Scott E.; Thummalapally, Damodar R., Electronic devices and systems, and methods for making and using the same.
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  45. Thompson, Scott E.; Thummalapally, Damodar R., Electronic devices and systems, and methods for making and using the same.
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  46. Tan,Chung Foong; Liu,Jinping; Lee,Hyeok Jae; Indajang,Bangun; Chor,Eng Fong; Ong,Shiang Yang, End of range (EOR) secondary defect engineering using substitutional carbon doping.
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  47. Ding, Yi, Fabrication of conductive gates for nonvolatile memories from layers with protruding portions.
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  48. Ding,Yi, Fabrication of conductive lines interconnecting conductive gates in nonvolatile memories, and non-volatile memory structures.
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  49. Ding,Yi, Fabrication of conductive lines interconnecting conductive gates in nonvolatile memories, and non-volatile memory structures.
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  50. Ding,Yi, Fabrication of conductive lines interconnecting first conductive gates in nonvolatile memories having second conductive gates provided by conductive gate lines, wherein the adjacent conductive gate l.
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  51. Ding,Yi, Fabrication of conductive lines interconnecting first conductive gates in nonvolatile memories having second conductive gates provided by conductive gate lines, wherein the adjacent conductive gate lines for the adjacent columns are spaced from each other, and non-volatile memory structures.
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  52. Ding,Yi, Fabrication of dielectric for a nonvolatile memory cell having multiple floating gates.
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  53. Ding, Yi, Fabrication of dielectric on a gate surface to insulate the gate from another element of an integrated circuit.
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  54. Ding,Yi, Fabrication of dielectric on a gate surface to insulate the gate from another element of an integrated circuit.
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  55. Ding, Yi, Fabrication of gate dielectric in nonvolatile memories having select, floating and control gates.
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  56. Ding, Yi, Fabrication of gate dielectric in nonvolatile memories having select, floating and control gates.
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  57. Ding,Yi, Fabrication of gate dielectric in nonvolatile memories in which a memory cell has multiple floating gates.
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  58. Ding,Yi, Fabrication of gate dielectric in nonvolatile memories in which a memory cell has multiple floating gates.
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  59. Ding,Yi, Fabrication of integrated circuit elements in structures with protruding features.
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  60. Radosavljevic, Marko; Datta, Suman; Doyle, Brian S.; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Majumdar, Amian; Chau, Robert S., Field effect transistor with metal source/drain regions.
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  61. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
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  62. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
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  63. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
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  64. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
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  65. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
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  66. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
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  67. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
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  68. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
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  69. Thompson, Scott E.; Shifren, Lucian; Ranade, Pushkar; Liu, Yujie; Kim, Sung Hwan; Wang, Lingquan; Zhao, Dalong; Bakhishev, Teymur; Hoffmann, Thomas; Pradhan, Sameer; Duane, Michael, High uniformity screen and epitaxial layers for CMOS devices.
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  70. Chang, Peter L. D.; Doyle, Brian S., Independently accessed double-gate and tri-gate transistors.
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  71. Chang, Peter L. D.; Doyle, Brian S., Independently accessed double-gate and tri-gate transistors in same process flow.
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  72. Chang, Peter L. D.; Doyle, Brian S., Independently accessed double-gate and tri-gate transistors in same process flow.
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  73. Clark, Lawrence T.; Kidd, David A.; Kuo, Augustine, Integrated circuit device body bias circuits and methods.
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  74. Clark, Lawrence T.; Kidd, David A.; Kuo, Augustine, Integrated circuit device body bias circuits and methods.
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  75. Clark, Lawrence T.; Kidd, David A.; Kuo, Augustine, Integrated circuit device body bias circuits and methods.
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  76. Wang, Jing, Integrated circuit device methods and models with predicted device metric variations.
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  77. Clark, Lawrence T.; Thompson, Scott E.; Roy, Richard S.; Rogenmoser, Robert; Thummalapally, Damodar R., Integrated circuit devices and methods.
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  78. Clark, Lawrence T.; Thompson, Scott E.; Roy, Richard S.; Rogenmoser, Robert; Thummalapally, Damodar R., Integrated circuit devices and methods.
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  79. Clark, Lawrence T.; Thompson, Scott E.; Roy, Richard S.; Rogenmoser, Robert; Thummalapally, Damodar R., Integrated circuit devices and methods.
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  80. Clark, Lawrence T.; Thompson, Scott E.; Roy, Richard S.; Rogenmoser, Robert; Thummalapally, Damodar R., Integrated circuit devices and methods.
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  81. Clark, Lawrence T.; Kidd, David A.; Chen, Chao-Wu, Integrated circuit process and bias monitors and related methods.
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  82. Clark, Lawrence T.; Kidd, David A.; Chen, Chao-Wu, Integrated circuit process and bias monitors and related methods.
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  83. Zhao, Dalong; Ranade, Pushkar; McWilliams, Bruce, Integrated circuits having a plurality of high-K metal gate FETs with various combinations of channel foundation structure and gate stack structure and methods of making same.
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  84. Zhao, Dalong; Ranade, Pushkar; McWilliams, Bruce, Integrated circuits having a plurality of high-K metal gate FETs with various combinations of channel foundation structure and gate stack structure and methods of making same.
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  85. Ding,Yi, Integrated circuits with openings that allow electrical contact to conductive features having self-aligned edges.
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  86. Shifren, Lucian; Ranade, Pushkar; Thompson, Scott E.; Sonkusale, Sachin R.; Zhang, Weimin, Low power semiconductor transistor structure and method of fabrication thereof.
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  87. Shifren, Lucian; Ranade, Pushkar; Thompson, Scott E.; Sonkusale, Sachin R.; Zhang, Weimin, Low power semiconductor transistor structure and method of fabrication thereof.
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  88. Shifren, Lucian; Ranade, Pushkar; Thompson, Scott E.; Sonkusale, Sachrin R.; Zhang, Weimin, Low power semiconductor transistor structure and method of fabrication thereof.
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  89. Clark, Lawrence T.; Leshner, Samuel, Memory circuits and methods of making and designing the same.
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  90. Bakhishev, Teymur; Pradhan, Sameer; Hoffmann, Thomas; Sonkusale, Sachin R., Method for fabricating a transistor device with a tuned dopant profile.
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  91. Bakhishev, Teymur; Pradhan, Sameer; Hoffmann, Thomas; Sonkusale, Sachin R., Method for fabricating a transistor device with a tuned dopant profile.
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  92. Bakhishev, Teymur; Pradhan, Sameer; Hoffmann, Thomas; Sonkusale, Sachin R., Method for fabricating a transistor device with a tuned dopant profile.
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  93. Thompson, Scott E.; Shifren, Lucian; Ranade, Pushkar; Liu, Yujie; Kim, Sung Hwan; Wang, Lingquan; Zhao, Dalong; Bakhishev, Teymur; Hoffmann, Thomas; Pradhan, Sameer; Duane, Michael, Method for fabricating a transistor with reduced junction leakage current.
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  94. Shifren, Lucian; Ranade, Pushkar; Hoffmann, Thomas; Thompson, Scott E., Method for fabricating multiple transistor devices on a substrate with varying threshold voltages.
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  95. Brask, Justin K.; Chau, Robert S.; Datta, Suman; Doczy, Mark L.; Doyle, Brian S.; Kavalieros, Jack T.; Majumdar, Amlan; Metz, Matthew V.; Radosavljevic, Marko, Method for fabricating transistor with thinned channel.
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  96. Brask, Justin K.; Chau, Robert S.; Datta, Suman; Doczy, Mark L.; Doyle, Brian S.; Kavalieros, Jack T.; Majumdar, Amlan; Metz, Matthew V.; Radosavljevic, Marko, Method for fabricating transistor with thinned channel.
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  97. Shifren, Lucian; Ema, Taiji, Method for reducing punch-through in a transistor device.
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  98. Brask, Justin K.; Doyle, Brian S.; Shah, Uday; Chau, Robert S., Method of patterning a film.
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  99. Ding,Yi, Methods of fabricating integrated circuits with openings that allow electrical contact to conductive features having self-aligned edges.
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  100. Thompson, Scott E.; Ranade, Pushkar; Scudder, Lance; Stager, Charles, Monitoring and measurement of thin film layers.
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  101. Roy, Richard S., Multiple VDD clock buffer.
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  102. Hoffmann, Thomas; Ranade, Pushkar; Shifren, Lucian; Thompson, Scott E., Multiple transistor types formed in a common epitaxial layer by differential out-diffusion from a doped underlayer.
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  103. Hoffmann, Thomas; Ranade, Pushkar; Shifren, Lucian; Thompson, Scott E., Multiple transistor types formed in a common epitaxial layer by differential out-diffusion from a doped underlayer.
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  104. Hoffmann, Thomas; Ranade, Pushkar; Shifren, Lucian; Thompson, Scott E., Multiple transistor types formed in a common epitaxial layer by differential out-diffusion from a doped underlayer.
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  105. Shah, Uday; Doyle, Brian S.; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
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  106. Shah, Uday; Doyle, Brian S.; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
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  107. Shah, Uday; Doyle, Brian S.; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
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  108. Shah, Uday; Doyle, Brian S.; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
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  109. Shah, Uday; Doyle, Brian; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
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  110. Shah, Uday; Doyle, Brian; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
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  111. Shah, Uday; Doyle, Brian; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
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  112. Hareland, Scott A.; Chau, Robert S.; Doyle, Brian S.; Rios, Rafael; Linton, Tom; Datta, Suman, Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication.
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  113. Hareland, Scott A.; Chau, Robert S.; Doyle, Brian S.; Rios, Rafael; Linton, Tom; Datta, Suman, Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication.
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  114. Brask, Justin K.; Dovle, Brian S.; Kavalleros, Jack; Doczy, Mark; Shah, Uday; Chau, Robert S., Nonplanar transistors with metal gate electrodes.
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  115. Ding, Yi, Nonvolatile memories and methods of fabrication.
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  116. Ding, Yi, Nonvolatile memories and methods of fabrication.
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  117. Ding,Yi, Nonvolatile memories and methods of fabrication.
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  118. Ding, Yi, Nonvolatile memories with a floating gate having an upward protrusion.
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  119. Ding,Yi, Nonvolatile memory cell with multiple floating gates formed after the select gate.
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  120. Ding,Yi, Nonvolatile memory cell with multiple floating gates formed after the select gate.
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  121. Ding,Yi, Nonvolatile memory cell with multiple floating gates formed after the select gate.
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  122. Ding,Yi, Nonvolatile memory cell with multiple floating gates formed after the select gate.
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  123. Ding, Yi, Nonvolatile memory cell with multiple floating gates formed after the select gate and having upward protrusions.
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  124. Ding,Yi, Nonvolatile memory cell with multiple floating gates formed after the select gate and having upward protrusions.
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  125. Ding,Yi, Nonvolatile memory cells with buried channel transistors.
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  126. Ding,Yi, Nonvolatile memory cells with buried channel transistors.
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  127. Kuo, Augustine, Operational amplifier input offset correction with transistor threshold voltage adjustment.
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