IPC분류정보
국가/구분 |
United States(US) Patent
등록
|
국제특허분류(IPC7판) |
|
출원번호 |
US-0614492
(2000-07-11)
|
발명자
/ 주소 |
- Forbes, Leonard
- Farrar, Paul A.
- Ahn, Kie Y.
|
출원인 / 주소 |
|
대리인 / 주소 |
Schwegman, Lundberg, Woessner & Kluth, P.A.
|
인용정보 |
피인용 횟수 :
17 인용 특허 :
99 |
초록
▼
A typical integrated-circuit fabrication requires interconnecting millions of microscopic transistors and resistors with aluminum wires. Making the aluminum wires flush, or coplanar, with underlying insulation requires digging trenches in the insulation, and then filling the trenches with aluminum t
A typical integrated-circuit fabrication requires interconnecting millions of microscopic transistors and resistors with aluminum wires. Making the aluminum wires flush, or coplanar, with underlying insulation requires digging trenches in the insulation, and then filling the trenches with aluminum to form the aluminum wires. Trench digging is time consuming and costly. Moreover, aluminum has higher electrical resistance than other metals, such as silver. Accordingly, the invention provides a new "self-trenching" or "self-planarizing" method of making coplanar silver wires. Specifically, one embodiment forms a first layer that includes silicon and germanium; oxidizes a region of the first layer to define an oxidized region and a non-oxidized region; and reacts silver with the non-oxidized region. The reaction substitutes, or replaces, the non-oxidized region with silver to form silver wires coplanar with the first layer. Another step removes germanium oxide from the oxidized region to form a porous insulation having a very low dielectric constant, thereby reducing capacitance. Thus, the present invention not only eliminates the timing-consuming, trench-digging step of conventional methods, but also reduces resistance and capacitance which, in turn, enable faster, more-efficient integrated circuits.
대표청구항
▼
A typical integrated-circuit fabrication requires interconnecting millions of microscopic transistors and resistors with aluminum wires. Making the aluminum wires flush, or coplanar, with underlying insulation requires digging trenches in the insulation, and then filling the trenches with aluminum t
A typical integrated-circuit fabrication requires interconnecting millions of microscopic transistors and resistors with aluminum wires. Making the aluminum wires flush, or coplanar, with underlying insulation requires digging trenches in the insulation, and then filling the trenches with aluminum to form the aluminum wires. Trench digging is time consuming and costly. Moreover, aluminum has higher electrical resistance than other metals, such as silver. Accordingly, the invention provides a new "self-trenching" or "self-planarizing" method of making coplanar silver wires. Specifically, one embodiment forms a first layer that includes silicon and germanium; oxidizes a region of the first layer to define an oxidized region and a non-oxidized region; and reacts silver with the non-oxidized region. The reaction substitutes, or replaces, the non-oxidized region with silver to form silver wires coplanar with the first layer. Another step removes germanium oxide from the oxidized region to form a porous insulation having a very low dielectric constant, thereby reducing capacitance. Thus, the present invention not only eliminates the timing-consuming, trench-digging step of conventional methods, but also reduces resistance and capacitance which, in turn, enable faster, more-efficient integrated circuits. heat sink and the wire. 2. The super low profile package according to claim 1, wherein a thickness of the die is approximately equal to a depth of the cavity. 3. The super low profile package according to claim 1, wherein a thickness of the die is smaller than a depth of the cavity. 4. The super low profile package according to claim 1, wherein a thickness of the substrate is approximately 0.2 mm. 5. The super low profile package according to claim 1, wherein a thickness of the heat sink is smaller than a height of the solder balls. 6. The super low profile package according to claim 5, wherein the thickness of the plastic mold over the first substrate surface is thinner than the height of the solder balls. 7. The super low profile package according to claim 1, wherein the heat sink is exposed to the outside of the plastic mold. 8. The super low profile package according to claim 7, wherein the super low profile package further connects to a printed circuit board (PCB), and the PCB has a ground layer, and the ground layer connects to the exposed heat sink. 9. The super low profile package according to claim 1, wherein the extending part of the heat sink adheres to the ground ring by epoxy. 10. The super low profile package according to claim 1, wherein the extending part of the heat sink adheres to the ground ring by solder. 11. The super low profile package according to claim 1, wherein a second substrate surface opposite the first substrate surface further includes a ground layer of the die and decreasing signal interference. 12. The super low profile package according to claim 11, wherein the ground layer is copper. 13. The super low profile package according to claim 1, wherein the cavity is filled with the plastic mold. 14. The super low profile package according to claim 1, wherein a second die surface of the die opposite to the first die surface is exposed to the atmosphere. 15. The super low profile package according to claim 1, wherein the heat sink further has a rectangular body shape. 16. The super low profile package according to claim 15, wherein the body is circularly shaped.
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