초록 ▼

A method and system for displaying a flight plan such that an entire flight plan is viewable through the use of scrolling devices is disclosed. The flight plan display may also include a method and system for collapsing and expanding a flight plan display, have provisions for the conspicuous marking

A method and system for displaying a flight plan such that an entire flight plan is viewable through the use of scrolling devices is disclosed. The flight plan display may also include a method and system for collapsing and expanding a flight plan display, have provisions for the conspicuous marking of changes to a flight plan, the use of tabs to switch between various displays of data, and access to a navigation database that allows a user to view information about various navigational aids. The database may also the access to the information about the navigational aids to be prioritized based on proximity to the current position of the aircraft.

대표청구항 ▼

A method and system for displaying a flight plan such that an entire flight plan is viewable through the use of scrolling devices is disclosed. The flight plan display may also include a method and system for collapsing and expanding a flight plan display, have provisions for the conspicuous marking

A method and system for displaying a flight plan such that an entire flight plan is viewable through the use of scrolling devices is disclosed. The flight plan display may also include a method and system for collapsing and expanding a flight plan display, have provisions for the conspicuous marking of changes to a flight plan, the use of tabs to switch between various displays of data, and access to a navigation database that allows a user to view information about various navigational aids. The database may also the access to the information about the navigational aids to be prioritized based on proximity to the current position of the aircraft. plied to said second surface of said printed circuit board, wherein the first and second solder masks further include a first plurality of openings larger than the conductive pads of the integrated circuit module and the printed circuit board, and a second plurality of openings smaller than the conductive pads of the integrated circuit module and the printed circuit board. 2. The semiconductor package of claim 1, wherein interconnections formed in areas where the mask opening is larger than the conductive pads are selectively placed in regions of high stress within the semiconductor package. 3. The semiconductor package of claim 1, wherein interconnections formed in areas where the mask opening is smaller than the conductive pads are located in regions of low stress within the semiconductor package. 4. The semiconductor package of claim 1, wherein an equilibrium height of the interconnections formed in areas where the mask opening is larger than the conductive pads is increased by the interconnections formed in areas where the mask opening is smaller than the conductive pads. 5. A substrate having a series of Ball Grid Array (BGA) interconnections formed on a plurality of conductive pads on a first surface of the substrate, and having a solder mask applied to the first surface of said substrate, wherein the mask further includes a first plurality of openings larger than the conductive pads, and a second plurality of openings smaller than the conductive pads. 6. The substrate of claim 5, wherein interconnections formed in areas where the mask opening is larger than the conductive pads are located in high stress areas of the substrate. 7. The substrate of claim 6, wherein the high stress areas of the substrate are at the edges of the substrate. 8. The substrate of claim 6, wherein the high stress areas of the substrate are at the corners and/or edges of the substrate. 9. The substrate of claim 5, wherein a majority of the BGA interconnections are formed wherein the mask openings are smaller than the conductive pads. 10. A solder mask, adapted to be coupled to a substrate having conductive pads thereon, and adapted to provide structure to a plurality of mask-defined solder joints, the solder mask having a first plurality of openings and a second plurality of openings, wherein the first plurality of openings are larger than the conductive pads and the second plurality of openings are smaller than the conductive pads. 11. The solder mask of claim 10, wherein the first plurality of openings are selectively located in high stress regions of the substrate, wherein high stress regions are selected from the group consisting of: the corners of the substrate, the edges of the substrate, the corners of the array of conductive pads, and the edges of the array of conductive pads. 12. The solder mask of claim 10, wherein a majority of the openings are selected from the second plurality of openings.