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Method for configuring peer-to-peer bus bridges in a computer system using shadow configuration registers

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-013/14
출원번호 US-0927407 (2001-08-10)
발명자 / 주소
  • Porterfield, A. Kent
출원인 / 주소
  • Micron Technology, Inc.
대리인 / 주소
    Dorsey & Whitney LLP
인용정보 피인용 횟수 : 12  인용 특허 : 26

초록

A method of configuring a computer system having a processor coupled by a host bus to first and second bus devices causes the processor to transmit on the host bus one or more configuration write commands that include configuration data representing a range of addresses assigned to the second bus de

대표청구항

A method of configuring a computer system having a processor coupled by a host bus to first and second bus devices causes the processor to transmit on the host bus one or more configuration write commands that include configuration data representing a range of addresses assigned to the second bus de

이 특허에 인용된 특허 (26)

  1. Walsh James J. ; Brown Jacqueline, Adaptive power management processes, circuits and systems.
  2. Kusters Norbert Paul, Apparatus for controlling an I/O port by queuing requests and in response to a predefined condition, enabling the I/O.
  3. Olarig Sompong P., Apparatus, method and system for a comuter CPU and memory to PCI bridge having a pluarlity of physical PCI buses.
  4. Lemon Steven P. (Los Gatos CA) Ross Patrick D. (Sunnyvale CA), Boot framework architecture for dynamic staged initial program load.
  5. Sheafor Stephen James ; Wei James Yuan, Bus arrangements for interconnection of discrete and/or integrated modules in a digital system and associated method.
  6. Kao Yen-Hsiung ; Lin Limas M. ; Chu Cyrus, Circuit and method for configuring a bus bridge using parameters from a supplemental parameter memory.
  7. Solomon Gary, Configuration data loopback in a bus bridge circuit.
  8. Shah Bakul V. (Palo Alto CA) Maskevitch James A. (Palo Alto CA), Data processing system having automatic configuration.
  9. Leavitt William I. ; Clemson Conrad R. ; Somers Jeffrey S. ; Chaves John M. ; Barbera David R. ; Clayton Shawn A., Digital data processing methods and apparatus for fault isolation.
  10. Wilson Malcolm Eric,GBX, Dynamically reconfigurable multi-function PCI adapter device.
  11. Rasmussen Norman J. ; Solomon Gary A. ; Carson David G. ; Hayek George R. ; Baxter Brent S. ; Case Colyn, High-throughput interconnect having pipelined and non-pipelined bus transaction modes.
  12. St. Clair Joe Christopher (Round Rock TX) Thurber Steven Mark (Austin TX), Information handling system for transmitting contents of line register from asynchronous controller to shadow register i.
  13. Young Bruce ; Coulson Rick, Intelligent bus bridge for input/output subsystems in a computer system.
  14. Blackledge John W. (Boca Raton FL) Cohen Ariel (Haifa ILX) Katz Sagi (Haifa ILX) Merkin Cindy M. (Lake Worth FL), Method and apparatus for configuring a bus-to-bus bridge.
  15. Garbus Elliott ; Davis Barry, Method and apparatus for enabling intelligent I/O subsystems using PCI I/O devices.
  16. Garbus Elliott ; Davis Barry, Method and apparatus for enabling intelligent I/O subsystems using PCI I/O devices.
  17. Gillespie Byron ; Goldschmidt Marc ; Sych Terry ; Young Bruce, Method and apparatus for interfacing a device compliant to a first bus protocol to an external bus having a second bus.
  18. Davis Barry R. ; Goble Scott, Method and apparatus providing programmable decode modes for secondary PCI bus interfaces.
  19. Gulick Dale E., Method for accessing control and status registers across a peer-peer bus.
  20. Leyda Jeff, Method for configuration of peripherals by interpreting response from peripherals to enable selection of driver file an.
  21. Gulick Dale E., Method for isochronous flow control across an inter-chip bus.
  22. MacLaren John M., Multi-threaded bus master.
  23. Lange Ronald Edwin, Selective data read-ahead in bus-to-bus bridge architecture.
  24. Hansen John P. ; Stence Ronald W. ; Typaldos Melanie D., System for performing DMA transfers where an interrupt request signal is generated based on the value of the last of a p.
  25. Kenny John D. ; Shah Pranay D., Transparent bridge between of a computer system and a method of interfacing the buses to operate as a single logical bus.
  26. Lin Fong Lu (David) ; Tsay Cherng-Yeuan (Henry) ; Doan David H., VL-bus/PCI-bus bridge.

이 특허를 인용한 특허 (12)

  1. Matsumoto, Munehisa; Kuno, Shinichiro, Bridge circuit for interfacing processor to main memory and peripherals.
  2. Nakayama, Keishi; Uehara, Keitaro; Aoyagi, Takashi; Toya, Shinichiro, Computer system and bus assignment method.
  3. Zimmer,Vincent J.; Rothman,Michael A., Managing peripheral device address space resources using a tunable bin-packing/knapsack algorithm.
  4. Zimmer,Vincent J.; Rothman,Michael A., Managing peripheral device address space resources using a tunable bin-packing/knapsack algorithm.
  5. Ervin,Joseph J., Method and apparatus for configuring multiple segment wired-AND bus systems.
  6. Ervin,Joseph J., Method and apparatus for constructing wired-and bus systems.
  7. Ervin, Joseph J., Method and apparatus for interconnecting wired-AND buses.
  8. Lindsay, Steven B.; Alvstad, Gary, Method and system for addressing a plurality of Ethernet controllers integrated into a single chip which utilizes a single bus interface.
  9. Ishimi, Koichi, Multi-processor device with groups of processors and respective separate external bus interfaces.
  10. Ishimi, Koichi, Multi-processor device with groups of processors consisting of respective separate external bus interfaces.
  11. Morgan, Donald M.; Merritt, Todd A., Multiple configuration multiple chip memory device and method.
  12. Morgan,Donald M.; Merritt,Todd A., Multiple configuration multiple chip memory device and method.
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