$\require{mediawiki-texvc}$

연합인증

연합인증 가입 기관의 연구자들은 소속기관의 인증정보(ID와 암호)를 이용해 다른 대학, 연구기관, 서비스 공급자의 다양한 온라인 자원과 연구 데이터를 이용할 수 있습니다.

이는 여행자가 자국에서 발행 받은 여권으로 세계 각국을 자유롭게 여행할 수 있는 것과 같습니다.

연합인증으로 이용이 가능한 서비스는 NTIS, DataON, Edison, Kafe, Webinar 등이 있습니다.

한번의 인증절차만으로 연합인증 가입 서비스에 추가 로그인 없이 이용이 가능합니다.

다만, 연합인증을 위해서는 최초 1회만 인증 절차가 필요합니다. (회원이 아닐 경우 회원 가입이 필요합니다.)

연합인증 절차는 다음과 같습니다.

최초이용시에는
ScienceON에 로그인 → 연합인증 서비스 접속 → 로그인 (본인 확인 또는 회원가입) → 서비스 이용

그 이후에는
ScienceON 로그인 → 연합인증 서비스 접속 → 서비스 이용

연합인증을 활용하시면 KISTI가 제공하는 다양한 서비스를 편리하게 이용하실 수 있습니다.

Image sensor of a quad flat package 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-031/0203
  • H01L-023/495
출원번호 US-0037895 (2001-10-22)
우선권정보 TW-90101003 A (2001-01-17)
발명자 / 주소
  • Huang, Chien-Ping
출원인 / 주소
  • Siliconware Precision Industries Co., Ltd.
대리인 / 주소
    J.C. Patents
인용정보 피인용 횟수 : 277  인용 특허 : 10

초록

An image sensor of a quad flat non-leaded package (QFN). The image sensor of a quad flat non-leaded package includes a lead frame having a plurality of leads and a die pad, and the leads are located around a periphery of the die pad. A molding structure is formed around an outer boundary of the lead

대표청구항

1. An image sensor of a quad flat non-leaded package (QFN), comprising: a lead frame having a plurality of leads and a die pad, wherein the leads are located around a periphery of the die pad, and the lead frame has a first surface and a corresponding second surface, each lead having a bonding po

이 특허에 인용된 특허 (10)

  1. Choi Sihn,KRX, Charge coupled device (CCD) semiconductor chip package.
  2. Yamanaka Hideo (Kanagawa JPX), Charge-coupled device image sensor.
  3. Fumio Hata JP; Tadashi Kosaka JP; Hisatane Komori JP, IC package having a conductive material at least partially filling a recess.
  4. Chien-Ping Huang TW, Leadless image sensor package structure and method for making the same.
  5. Kurihara Kenichi (Tokyo JPX), Plastic encapsulated semiconductor device having wing leads.
  6. Glenn Thomas P., Plastic package for an optical integrated circuit device and method of making.
  7. Chin-Yuan Hung TW; Lien-Chen Chiang TW; Cheng-Shiu Hsiao TW, Quad flat non-leaded package structure for housing CMOS sensor.
  8. Chien-Ping Huang TW, Semiconductor package configuration based on lead frame having recessed and shouldered portions for flash prevention.
  9. Kitaoka Kouki (Sakurai JPX) Maeda Takamichi (Ikoma JPX) Minamide Shozo (Naga-ken JPX), Solid state imaging device having a solid state image sensor and its peripheral IC mounted on one package.
  10. Hirose Shinichi,JPX ; Mizuno Naohito,JPX, Structure for mounting electronic components and method for mounting the same.

이 특허를 인용한 특허 (277)

  1. Sirinorakul, Saravuth, Apparatus for and methods of attaching heat slugs to package tops.
  2. Railkar, Tarak A.; Anderson, Kevin J.; Meliane, Walid; Beall, John M., Apparatuses, systems, and methods for die attach coatings for semiconductor packages.
  3. Vig, Ravi; David, Paul A.; Shoemaker, Eric G., Arrangements for magnetic field sensors that act as movement detectors.
  4. Taylor, William P.; Scheller, P. Karl; David, Paul, Arrangements for magnetic field sensors that act as tooth detectors.
  5. Taylor, William P.; Scheller, P. Karl; David, Paul A., Arrangements for magnetic field sensors that act as tooth detectors.
  6. David, Paul A.; Shoemaker, Eric G.; Eagen, Jeffrey, Arrangements for magnetic field sensors to cancel offset variations.
  7. Sirinorakul, Saravuth, Auxiliary leadframe member for stabilizing the bond wire process.
  8. Sirinorakul, Saravuth, Auxiliary leadframe member for stabilizing the bond wire process.
  9. Huemoeller, Ronald Patrick; Kelly, Michael; Hiner, David Jon, Backside warpage control structure and fabrication method.
  10. d'Estries,Maximilien, Cavity case with clip/plug for use on multi-media card.
  11. Jang, Sang Jae; Park, Chul Woo; Kim, Jae Dong; Lee, Choon Heung, Chamfered memory card module and method of making same.
  12. Pan, Yu-Tang; Chou, Shih-Wen, Chip package structure and manufacturing method thereof.
  13. Do, Won Chul; Ko, Yong Jae, Conductive pad on protruding through electrode.
  14. Do, Won Chul; Ko, Yong Jae, Conductive pad on protruding through electrode semiconductor device.
  15. Do, Won Chul; Ko, Yong Jae, Conductive pad on protruding through electrode semiconductor device.
  16. Davis, Terry W.; Son, Sun Jin, Conformal shield on punch QFN semiconductor package.
  17. McConville, Paul J.; Lefevre, Jason M.; Moore, Steven R.; Herrmann, Douglas K., Cooling control system.
  18. Miks, Jeffrey Alan; Miranda, John A., Die down multi-media card and method of making same.
  19. Miks,Jeffrey Alan; Miranda,John A., Die down multi-media card and method of making same.
  20. Berry, Christopher John; Huemoeller, Ronald Patrick; Hiner, David Jon, Direct-write wafer level chip scale package.
  21. Berry, Christopher John; Huemoeller, Ronald Patrick; Hiner, David Jon, Direct-write wafer level chip scale package.
  22. Berry, Christopher John; Huemoeller, Ronald Patrick; Hiner, David Jon, Direct-write wafer level chip scale package.
  23. Alegre, Sherwin; Romero, Rommel B.; Antivola, Febie; Echegoyen, Jaime H., Double downset double dambar suspended leadframe.
  24. Park, Chul Woo; Ko, Suk Gu; Jang, Sang Jae; Park, Sung Su; Lee, Choon Heung, Double mold memory card and its manufacturing method.
  25. Berry, Christopher J., Dual laminate package structure with embedded elements.
  26. Berry, Christopher J., Dual laminate package structure with embedded elements.
  27. Berry, Christopher J., Dual laminate package structure with embedded elements.
  28. Huemoeller, Ronald Patrick; Rusli, Sukianto; Razu, David, Electronic component package comprising fan-out and fan-in traces.
  29. Huemoeller, Ronald Patrick; Kelly, Michael; Hiner, David Jon, Embedded component package and fabrication method.
  30. Huemoeller, Ronald Patrick; Kelly, Michael; Hiner, David Jon, Embedded component package and fabrication method.
  31. Huemoeller, Ronald Patrick; Rusli, Sukianto; Hiner, David J., Embedded electronic component package.
  32. Huemoeller, Ronald P.; Rusli, Sukianto; Hiner, David Jon, Embedded electronic component package fabrication method.
  33. Sheridan,Richard Peter; Huemoeller,Ronald Patrick; Hiner,David Jon; Rusli,Sukianto, Embedded leadframe semiconductor package.
  34. Van Gemert, Leonardus Antonius Elisabeth; Kamphuis, Tonny; Buenning, Hartmut; Zenz, Christian, Encapsulated wafer-level chip scale (WLSCP) pedestal packaging.
  35. Pichler,Karl, Encapsulation of thin-film electronic devices.
  36. Jang,Sang Jae; Park,Chul Woo; Lee,Choon Heung, Enhanced durability memory card.
  37. Berry, Christopher J.; Scanlan, Christopher M.; Faheem, Faheem F., Etch singulated semiconductor package.
  38. Berry,Christopher J.; Scanlan,Christopher M.; Faheem,Faheem F., Etch singulated semiconductor package.
  39. Foster,Donald C., Exposed lead QFP package fabricated through the use of a partial saw process.
  40. Scanlan, Christopher M.; St. Amand, Roger D.; Kim, Jae Dong, Fan out build up substrate stackable package and method.
  41. Davis,Terry W., Fan-in leadframe semiconductor package.
  42. Choi, YeonHo; Olson, Timothy L., Flat semiconductor package with half package molding.
  43. Sirinorakul, Saravuth; Nondhasitthichai, Somchai, Flip chip cavity package.
  44. Sirinorakul, Saravuth; Nondhasitthichai, Somchai, Flip chip cavity package.
  45. Choi, YeonHo; Kim, GiJeong; Kim, WanJong, Fusion quad flat semiconductor package.
  46. Choi, YeonHo; Kim, GiJeong; Kim, WanJong, Fusion quad flat semiconductor package.
  47. Chuang, Cheng-Lung; Lin, Chi-Cheng, Image sensing device and packaging method thereof.
  48. Tsai,Ming Chiang; Lee,Chun Yu; Jiang,Tsung Wei, Image sensor package and system.
  49. Kim, Gi Jeong; Choi, Yeon Ho; Kim, Wan Jong, Increased I/O leadframe and semiconductor device including same.
  50. Kim, Gi Jeong; Choi, Yeon Ho; Kim, Wan Jong, Increased I/O leadframe and semiconductor device including same.
  51. Lee, Chang Deok; Na, Do Hyun, Increased I/O semiconductor package and method of making same.
  52. Yang,Sung Jin; Moon,Doo Hwan; Shin,Won Dai, Increased capacity leadframe and semiconductor package using the same.
  53. Kim, Jae Yoon; Kim, Gi Jeong; Moon, Myung Soo, Increased capacity semiconductor package.
  54. Fusaro,James M.; Darveaux,Robert F.; Rodriguez,Pablo, Integrated circuit device packages and substrates for making the packages.
  55. Glenn, Thomas P., Integrated circuit package and method of making the same.
  56. Glenn, Thomas P., Integrated circuit package and method of making the same.
  57. Glenn, Thomas P., Integrated circuit package and method of making the same.
  58. Glenn, Thomas P., Integrated circuit package and method of making the same.
  59. Glenn, Thomas P., Integrated circuit package and method of making the same.
  60. David, Paul; Taylor, William P.; Scheller, P. Karl; Vig, Ravi; Friedrich, Andreas P., Integrated circuit package having a split lead frame.
  61. Taylor, William P.; David, Paul; Vig, Ravi, Integrated circuit package having a split lead frame.
  62. David, Paul; Vig, Ravi; Taylor, William P.; Friedrich, Andreas P., Integrated circuit package having a split lead frame and a magnet.
  63. Camacho, Zigmund Ramirez; Bathan, Henry Descalzo; Caparas, Jose Alvin; Trasporto, Arnel, Integrated circuit package system with lead support.
  64. Fuentes, Ruben; Dunlap, Brett, Integrated passive device structure and method.
  65. d'Estries,Maximilien; Shermer,Stephen G.; Miks,Jeffrey A., Interposer for interconnecting components in a memory card.
  66. Nondhasitthichai, Somchai; Sirinorakul, Saravuth; Kongthaworn, Kasemsan; Suwannaset, Vorajit, Lead frame ball grid array with traces under die.
  67. Nondhasitthichai, Somchai; Sirinorakul, Saravuth; Kongthaworn, Kasemsan; Suwannaset, Vorajit, Lead frame ball grid array with traces under die.
  68. Sirinorakul, Saravuth, Lead frame ball grid array with traces under die having interlocking features.
  69. Sirinorakul, Saravuth, Lead frame ball grid array with traces under die having interlocking features.
  70. Lee, Hyung Ju, Lead frame for semiconductor package.
  71. Lee,Hyung Ju, Lead frame for semiconductor package.
  72. Nondhasittichai, Somchai; Sirinorakul, Saravuth, Lead frame land grid array.
  73. Nondhasitthichai, Somchai; Sirinorakul, Saravuth; Kongthaworn, Kasemsan; Suwannaset, Vorajit, Lead frame land grid array with routing connector trace under unit.
  74. Nondhasitthichai, Somchai; Sirinorakul, Saravuth; Kongthaworn, Kasemsan; Suwannaset, Vorajit, Lead frame land grid array with routing connector trace under unit.
  75. Miks,Jeffrey Alan; Kaskoun,Kenneth; Liebhard,Markus; Foster,Donald Craig; Hoffman,Paul Robert; Bertholio,Frederic, Lead-frame method and assembly for interconnecting circuits within a circuit module.
  76. Ahn, Byung Hoon; Ku, Jae Hun; Chung, Young Suk; Ko, Suk Gu; Jang, Sung Sik; Choi, Young Nam; Do, Won Chul, Leadframe and semiconductor package made using the leadframe.
  77. Ahn, Byung Hoon; Ku, Jae Hun; Chung, Young Suk; Ko, Suk Gu; Jang, Sung Sik; Choi, Young Nam; Do, Won Chul, Leadframe and semiconductor package made using the leadframe.
  78. Ahn,Byung Hoon; Ku,Jae Hun; Chung,Young Suk; Ko,Suk Gu; Jang,Sung Sik; Choi,Young Nam; Do,Won Chul, Leadframe and semiconductor package made using the leadframe.
  79. Sirinorakul, Saravuth, Leadframe based multi terminal IC package.
  80. Sirinorakul, Saravuth, Leadframe based multi terminal IC package.
  81. Sirinorakul, Saravuth; Yenrudee, Suebphong, Leadframe feature to minimize flip-chip semiconductor die collapse during flip-chip reflow.
  82. Lee, Hyung Ju, Leadframe for semiconductor package.
  83. Edwards, Keith M.; Gillett, Blake A., Leadframe package for semiconductor devices.
  84. Kuo, Bob Shih Wei; Nickelsen, Jr., John Merrill; Olson, Timothy L., Leadframe structure for concentrated photovoltaic receiver package.
  85. Kim,Gi Jeong; Kim,Jin Han; Oh,Jin Seok, Leadframe type semiconductor package having reduced inductance and its manufacturing method.
  86. Boon,Suan Jeung; Chia,Yong Poo; Neo,Yong Loo; Chua,Swee Kwang; Low,Siu Waf, Leadless packaging for image sensor devices.
  87. Pan,Yu Tang; Chou,Shih Wen; Liu,Men Shew, Light emitting chip package and manufacturing method thereof.
  88. Kromotis,Patrick; Waitl,G��nter, Light source module and method for production thereof.
  89. Drouin, Mathew; Fernandez, Devon; Towne, Jay M.; Milesi, Alejandro G., Magnetic field sensor and electronic circuit that pass amplifier current through a magnetoresistance element.
  90. Foletto, Andrea; Eagen, Jeffrey; David, Paul A., Magnetic field sensor for sensing a movement of a ferromagnetic target object.
  91. Foletto, Andrea; Vuillermet, Yannick; Friedrich, Andreas P., Magnetic field sensor for sensing a movement of a target object.
  92. David, Paul A.; Vig, Ravi, Magnetic field sensor for sensing a proximity of an object.
  93. Vig, Ravi; Taylor, William P.; David, Paul A.; Scheller, P. Karl; Friedrich, Andreas P., Magnetic field sensor integrated circuit with an electromagnetic suppressor.
  94. Vig, Ravi; Taylor, William P.; David, Paul; Scheller, P. Karl; Friedrich, Andreas P., Magnetic field sensor integrated circuit with integral ferromagnetic material.
  95. Vig, Ravi; Taylor, William P.; Friedrich, Andreas P.; David, Paul; Lo, Marie-Adelaide; Burdette, Eric; Shoemaker, Eric; Doogue, Michael C., Magnetic field sensor integrated circuit with integral ferromagnetic material.
  96. David, Paul A.; Taylor, William P., Magnetic field sensor providing a movement detector.
  97. Ararao, Virgil; Sharma, Nirmal; Engel, Raymond W.; Gagnon, Jay; Sauber, John; Taylor, William P.; Kam-Lum, Elsa, Magnetic field sensors and methods for fabricating the magnetic field sensors.
  98. Ararao, Virgil; Sharma, Nirmal; Engel, Raymond W.; Gagnon, Jay; Sauber, John; Taylor, William P.; Kam-Lum, Elsa, Magnetic field sensors and methods for fabricating the magnetic field sensors.
  99. Miks,Jeffrey Alan; Zwenger,Curtis Michael; Gogue,Brenda Concepcion; Shermer,Stephen Gregory; d'Estries,Maximilien Jouchin, Memory card ESC substrate insert.
  100. Park,Chul Woo; Jang,Sang Jae; Park,Sung Su; Lee,Choon Heung; Ko,Suk Gu, Memory card and its manufacturing method.
  101. Park,Chul Woo; Jang,Sang Jae; Park,Sung Su; Lee,Choon Heung; Ko,Suk Gu, Memory card and its manufacturing method.
  102. Benjavasukul, Woraya; Somrubpornpinan, Thipyaporn; Charapaka, Panikan, Metallic solderability preservation coating on metal part of semiconductor package to prevent oxide.
  103. Benjavasukul, Woraya; Somrubpornpinan, Thipyaporn; Charapaka, Panikan, Metallic solderability preservation coating on metal part of semiconductor package to prevent oxide.
  104. Benjavasukul, Woraya; Somrubpornpinan, Thipyaporn; Charapaka, Panikan, Metallic solderability preservation coating on metal part of semiconductor package to prevent oxide.
  105. David, Paul; Taylor, William P., Method and apparatus for magnetic sensor producing a changing magnetic field.
  106. Sirinorakul, Saravuth; Nondhasitthichai, Somchai, Method and apparatus for no lead semiconductor package.
  107. Davis,Terry W., Method for fabricating a fan-in leadframe semiconductor package.
  108. Huang,Chien Ping, Method for fabricating a photosensitive semiconductor package.
  109. Nondhasitthichai, Somchai; Sirinorakul, Saravuth, Method for forming lead frame land grid array.
  110. Minamio,Masanori; Sano,Hikari, Method for manufacturing solid-state imaging devices.
  111. Yow, Kai Yun; Eu, Poh Leng, Method of assembling pressure sensor device.
  112. Dunlap, Brett Arnold, Method of forming a plurality of electronic component packages.
  113. Edwards,Keith M.; Gillett,Blake A., Method of making a leadframe for semiconductor devices.
  114. Glenn,Thomas P., Method of making an integrated circuit package.
  115. Glenn,Thomas P., Method of making an integrated circuit package.
  116. Glenn,Thomas P., Method of making an integrated circuit package.
  117. Nguyen,Hau Thanh; Kelkar,Nikhil, Method to dispense light blocking material for wafer level CSP.
  118. Pepka, Gary T.; Taylor, William P., Methods and apparatus for magnetic sensor having integrated coil.
  119. Milano, Shaun D.; Doogue, Michael C.; Taylor, William P., Methods and apparatus for magnetic sensor having non-conductive die paddle.
  120. Milano, Shaun D.; Doogue, Michael C.; Taylor, William P., Methods and apparatus for magnetic sensor having non-conductive die paddle.
  121. Milano, Shaun D.; Doogue, Michael C.; Taylor, William P., Methods and apparatus for magnetic sensor having non-conductive die paddle.
  122. Metivier, Ryan; Taylor, William P., Methods and apparatus for magnetic sensors having highly uniform magnetic fields.
  123. Engel, Raymond W.; Sharma, Nirmal; Taylor, William P., Methods and apparatus for multi-stage molding of integrated circuit package.
  124. Engel, Raymond W.; Sharma, Nirmal; Taylor, William P., Methods for multi-stage molding of integrated circuit package.
  125. Bolken, Todd O.; Cobbley, Chad A., Methods for packaging image sensitive electronic devices.
  126. Bolken,Todd O.; Cobbley,Chad A., Methods for packaging image sensitive electronic devices.
  127. Bolken,Todd O.; Cobbley,Chad A., Methods for packaging image sensitive electronic devices.
  128. Bolken,Todd O.; Cobbley,Chad A., Methods for packaging image sensitive electronic devices.
  129. Sirinorakul, Saravuth; Yenrudee, Suebphong, Methods of manufacturing semiconductor devices including terminals with internal routing interconnections.
  130. Jeon, Hyeong Il; Chung, Hyung Kook; Kim, Hong Bae; Kim, Byong Jin, Micro lead frame structure having reinforcing portions and method.
  131. Jeon, Hyeong Il; Chung, Hyung Kook; Kim, Hong Bae; Kim, Byong Jin, Micro lead frame structure having reinforcing portions and method.
  132. Jang, Sang Jae; Park, Chul Woo; Lee, Choon Heung, Modular memory card and method of making same.
  133. Nondhasitthichai, Somchai; Sirinorakul, Saravuth, Molded leadframe substrate semiconductor package.
  134. Nondhasitthichai, Somchai; Sirinorakul, Saravuth, Molded leadframe substrate semiconductor package.
  135. Nondhasitthichai, Somchai; Sirinorakul, Saravuth, Molded leadframe substrate semiconductor package.
  136. Nondhasitthichai, Somchai; Sirinorakul, Saravuth, Molded leadframe substrate semiconductor package.
  137. Nondhasitthichai, Somchai; Sirinorakul, Saravuth, Molded leadframe substrate semiconductor package.
  138. Nondhasitthichai, Somchai; Sirinorakul, Saravuth, Molded leadframe substrate semiconductor package.
  139. Sirinorakul, Saravuth; Nondhasitthichai, Somchai, Molded leadframe substrate semiconductor package.
  140. Sirinorakul, Saravuth; Nondhasitthichai, Somchai, Molded leadframe substrate semiconductor package.
  141. Jang,Sang Jae; Park,Chul Woo; Choi,Jong Woon; Kim,Jae Dong; Lee,Choon Heung; Lee,Chang Deok, Multiple cover memory card.
  142. Bancod, Ludovico; Dela Cruz, Gregorio G.; Canoy, Fidelyn R.; Alabin, Leocadio M., Offset etched corner leads for semiconductor package.
  143. Camacho, Zigmund R.; Bathan, Henry D.; Tay, Lionel Chien Hui; Trasporto, Arnel Senosa, Optical semiconductor device having pre-molded leadframe with window and method therefor.
  144. Camacho, Zigmund R.; Bathan, Henry D.; Tay, Lionel Chien Hui; Trasporto, Arnel Senosa, Optical semiconductor device having pre-molded leadframe with window and method therefor.
  145. Camacho, Zigmund R; Bathan, Henry D; Tay, Lionel Chien Hui; Trasporto, Amel Senosa, Optical semiconductor device having pre-molded leadframe with window and method therefor.
  146. Fujitomo, Masato; Tamaki, Hiroto; Nishijima, Shinji; Tanda, Yuichiro; Miki, Tomohide, Optical-semiconductor device and method for manufacturing the same.
  147. Fujitomo, Masato; Tamaki, Hiroto; Nishijima, Shinji; Tanda, Yuichiro; Miki, Tomohide, Optical-semiconductor device and method for manufacturing the same.
  148. Fujitomo, Masato; Tamaki, Hiroto; Nishijima, Shinji; Tanda, Yuichiro; Miki, Tomohide, Optical-semiconductor device with bottom surface including electrically conductive members and light-blocking base member therebetween, and method for manufacturing the same.
  149. Kinsman, Larry D., Optically interactive device package array.
  150. Roa, Fernando; St. Amand, Roger D., Package in package device for RF transceiver module.
  151. Roa, Fernando; St. Amand, Roger D., Package in package device for RF transceiver module.
  152. Kang, Dae Byoung; Yang, Sung Jin; Ok, Jung Tae; Kim, Jae Dong, Package in package semiconductor device.
  153. Hwang, Chan Ha; Sohn, Eun Sook; Choi, Ho; Kim, Byong Jin; Yu, Ji Yeon; Lee, Min Woo, Package in package semiconductor device with film over wire.
  154. Lin, Pang-Chun; Hung, Hsiao-Jen; Li, Chun-Yuan; Huang, Chien-Ping; Ke, Chun-Chi, Package structure.
  155. Sirinorakul, Saravuth; Nondhasitthichai, Somchai, Package with heat transfer.
  156. Sirinorakul, Saravuth; Nondhasitthichai, Somchai, Package with heat transfer.
  157. Barlow, Arthur, Panelized process for SMT sensor devices.
  158. Hung,Chia Yu; Huang,Chien Ping; Yang,Ke Chuan, Photosensitive semiconductor package and method for fabricating the same.
  159. Huang,Chien Ping, Photosensitive semiconductor package, method for fabricating the same, and lead frame thereof.
  160. Glenn,Thomas P., Plastic integrated circuit package and method and leadframe for making the package.
  161. Glenn,Thomas P., Plastic integrated circuit package and method and leadframe for making the package.
  162. Sirinorakul, Saravuth, Plated terminals with routing interconnections semiconductor device.
  163. Sirinorakul, Saravuth, Plated terminals with routing interconnections semiconductor device.
  164. Sirinorakul, Saravuth, Plated terminals with routing interconnections semiconductor device.
  165. Sirinorakul, Saravuth, Plated terminals with routing interconnections semiconductor device.
  166. Sirinorakul, Saravuth, Post-mold for semiconductor package having exposed traces.
  167. Sirinorakul, Saravuth, Post-mold for semiconductor package having exposed traces.
  168. Miks, Jeffrey Alan; Schoonejongen, Ronald James, Pre-molded leadframe.
  169. Miks,Jeffrey Alan; Schoonejongen,Ronald James, Pre-molded leadframe.
  170. Diot,Jean Luc; Teysseyre,Jerome, Process for fabricating a semiconductor package and semiconductor package with leadframe.
  171. Sirinorakul, Saravuth; Yenrudee, Suebphong, Protruding terminals with internal routing interconnections semiconductor device.
  172. Cadag, Aaron; Antilano, Jr., Ernesto; Cadag, Ela Mia, QFN pre-molded leadframe having a solder wettable sidewall on each lead.
  173. Kim, Bong Chan; Kim, Do Hyung; Hwang, Chan Ha; Lee, Min Woo; Sohn, Eun Sook; Kang, Won Joon, Reduced profile stackable semiconductor package.
  174. Kim, Bong Chan; Na, Jae Young; Song, Jae Kyu, Reduced size stacked semiconductor package and method of making the same.
  175. Koike,Masahiro; Narita,Hirochika, Resin molded semiconductor device.
  176. Koike,Masahiro; Narita,Hirochika, Resin molded semiconductor device and mold.
  177. Satoh, Masayuki; Maemura, Koshi, Resin-sealed semiconductor device and method of manufacturing the same.
  178. Jiao, Jinbao, Seal apparatus and method of manufacturing the same.
  179. Miks,Jeffrey Alan, Secure digital memory card using land grid array structure.
  180. Miks,Jeffrey Alan; Bancod,Ludovico E., Secure digital memory card using land grid array structure.
  181. Miks,Jeffrey Alan; Bancod,Ludovico E., Secure digital memory card using land grid array structure.
  182. Kim, Sang Won; Jung, Boo Yang; Kim, Sung Kyu; Yoo, Min; Lee, Seung Jae, Semiconductor device and fabricating method thereof.
  183. Do, Won Chul; Jung, Yeon Seung; Ko, Yong Jae, Semiconductor device and manufacturing method thereof.
  184. Shirasaka,Kenichi; Saitoh,Hiroshi, Semiconductor device and package, and method of manufacture therefor.
  185. Shirasaka, Kenichi; Saitoh, Hiroshi, Semiconductor device and package, and method of manufacturer therefor.
  186. Do, Won Chul; Ko, Yong Jae, Semiconductor device comprising a conductive pad on a protruding-through electrode.
  187. Lee, Beng Siong; Teh, Guat Kew; Wong, Wai Keong, Semiconductor device having die pads isolated from interconnect portion and method of assembling same.
  188. Do, Won Chul; Jung, Yeon Seung; Ko, Yong Jae, Semiconductor device having through electrodes protruding from dielectric layer.
  189. Kim, Gwang Ho; Kim, Jin Seong; Park, Dong Joo; Kang, Dae Byoung, Semiconductor device including increased capacity leadframe.
  190. Kim, Gi Jeong; Choi, Yeon Ho, Semiconductor device including leadframe having power bars and increased I/O.
  191. Kim, Gi Jeong; Choi, Yeon Ho, Semiconductor device including leadframe having power bars and increased I/O.
  192. Bae, Jae Min; Kim, Byong Jin; Bang, Won Bae, Semiconductor device including leadframe with a combination of leads and lands.
  193. Bae, Jae Min; Kim, Byong Jin; Bang, Won Bae, Semiconductor device including leadframe with a combination of leads and lands and method.
  194. Bae, Jae Min; Kim, Byong Jin; Bang, Won Bae, Semiconductor device including leadframe with a combination of leads and lands and method.
  195. Bae, Jae Min; Kim, Byong Jin; Bang, Won Bae, Semiconductor device including leadframe with a combination of leads and lands and method.
  196. Bae, Jae Min; Kim, Byong Jin; Bang, Won Bae, Semiconductor device including leadframe with a combination of leads and lands and method.
  197. Kim, Gi Jeong; Kim, Jae Yoon; Lee, Kyu Won, Semiconductor device including leadframe with downsets.
  198. Choi, Yeon Ho; Kim, GiJeong; Kim, WanJong, Semiconductor device including leadframe with increased I/O.
  199. Choi, Yeon Ho; Kim, GiJeong; Kim, WanJong, Semiconductor device including leadframe with increased I/O.
  200. Kim, Gi Jeong; Kim, Wan Jong, Semiconductor device with increased I/O leadframe.
  201. Kim, Gi Jeong; Kim, Wan Jong, Semiconductor device with increased I/O leadframe.
  202. Kim, Wan Jong; Do, Young Tak; Cho, Byong Woo, Semiconductor device with increased I/O leadframe including power bars.
  203. Kim, Hong Bae; Kim, Hyun Jun; Chung, Hyung Kook, Semiconductor device with leadframe configured to facilitate reduced burr formation.
  204. Kim, Hyun Jun; Chung, Hyung Kook; Kim, Hong Bae, Semiconductor device with leadframe configured to facilitate reduced burr formation.
  205. Kwang, Chua Swee; Chia, Yong Poo, Semiconductor dies with recesses, associated leadframes, and associated systems and methods.
  206. Kwang, Chua Swee; Chia, Yong Poo, Semiconductor dies with recesses, associated leadframes, and associated systems and methods.
  207. Seo, Seong Min; Chung, Young Suk; Paek, Jong Sik; Ku, Jae Hun; Yee, Jae Hak, Semiconductor package.
  208. Kim,Do Hyung; Jeon,Hyung Il; Park,Doo Hyun, Semiconductor package and its manufacturing method.
  209. Yee, Jae Hak; Chung, Young Suk; Lee, Jae Jin; Davis, Terry; Han, Chung Suk; Ku, Jae Hun; Kwak, Jae Sung; Ryu, Sang Hyun, Semiconductor package and method of making using leadframe having lead locks to secure leads to encapsulant.
  210. Jeon, Hyung Il; Chung, Ji Young; Kim, Byong Jin; Park, In Bae; Bae, Jae Min; Park, No Sun, Semiconductor package and method therefor.
  211. Jeon, Hyung Il; Chung, Ji Young; Kim, Byong Jin; Park, In Bae; Bae, Jae Min; Park, No Sun, Semiconductor package and method therefor.
  212. Jang, Sung Sik, Semiconductor package having improved adhesiveness and ground bonding.
  213. Jang,Sung Sik, Semiconductor package having improved adhesiveness and ground bonding.
  214. Smith, Lee J., Semiconductor package having leadframe with exposed anchor pads.
  215. Smith, Lee J., Semiconductor package having leadframe with exposed anchor pads.
  216. Lee,Tae Heon; Seo,Mu Hwan, Semiconductor package having reduced thickness.
  217. Lee,Tae Heon; Seo,Mu Hwan, Semiconductor package having reduced thickness.
  218. Paek,Jong Sik, Semiconductor package including flip chip.
  219. Perez, Erasmo; Roman, David T., Semiconductor package with exposed die pad and body-locking leadframe.
  220. St. Amand, Roger D.; Perelman, Vladimir, Semiconductor package with fast power-up cycle and method of making same.
  221. Sirinorakul, Saravuth, Semiconductor package with full plating on contact side surfaces and methods thereof.
  222. Lee, Chang Deok; Na, Do Hyun, Semiconductor package with half-etched locking features.
  223. Park, Doo Hyun; Kim, Jae Yoon; Jung, Yoon Ha, Semiconductor package with increased I/O density and method of making same.
  224. Park, Doo Hyun; Kim, Jae Yoon; Jung, Yoon Ha, Semiconductor package with increased I/O density and method of making the same.
  225. Lee,Choon Heung; Foster,Donald C.; Choi,Jeoung Kyu; Kim,Wan Jong; Youn,Kyong Hoon; Lee,Sang Ho; Lee,Sun Goo, Semiconductor package with increased number of input and output pins.
  226. Chuang,Jui Yu; Chan,Lien Chi; Huang,Chih Ming, Semiconductor package with lead frame as chip carrier and method for fabricating the same.
  227. Sirinorakul, Saravuth; Yenrudee, Suebphong, Semiconductor package with multiple molding routing layers and a method of manufacturing the same.
  228. Sirinorakul, Saravuth; Yenrudee, Suebphong, Semiconductor package with multiple molding routing layers and a method of manufacturing the same.
  229. Sirinorakul, Saravuth; Yenrudee, Suebphong, Semiconductor package with multiple molding routing layers and a method of manufacturing the same.
  230. Sirinorakul, Saravuth; Yenrudee, Suebphong, Semiconductor package with multiple molding routing layers and a method of manufacturing the same.
  231. Sirinorakul, Saravuth; Yenrudee, Suebphong, Semiconductor package with multiple molding routing layers and a method of manufacturing the same.
  232. Sirinorakul, Saravuth; Yenrudee, Suebphong, Semiconductor package with multiple molding routing layers and a method of manufacturing the same.
  233. Kim, Do Hyeong; Kim, Bong Chan; Kim, Yoon Joo; Chung, Ji Young, Semiconductor package with patterning layer and method of making same.
  234. Yenrudee, Suebphong; Kongpoung, Chanapat; Hongsongkiat, Sant; Ounkaew, Siriwanna; Injan, Chatchawan; Sirinorakul, Saravuth, Semiconductor package with plated metal shielding and a method thereof.
  235. Jeong, Jung Tae, Semiconductor packages including interconnection members.
  236. Holzmann, Martin; Ohl, Christian; Emmerich, Harald, Sensor module.
  237. Choi, Yeon Ho, Side leaded, bottom exposed pad and bottom exposed lead fusion quad flat semiconductor package.
  238. Choi, Yeon Ho, Side leaded, bottom exposed pad and bottom exposed lead fusion quad flat semiconductor package.
  239. Mok, Seung Kon; Ro, Young Hoon, Solid-state imaging apparatus, wiring substrate and methods of manufacturing the same.
  240. Shimizu, Katsutoshi; Minamio, Masanori; Yamauchi, Kouichi, Solid-state imaging device and method for manufacturing the same.
  241. Shimizu,Katsutoshi; Minamio,Masanori; Yamauchi,Kouichi, Solid-state imaging device and method for manufacturing the same.
  242. Heo, Byong II, Stackable semiconductor package having partially exposed semiconductor die and method of fabricating the same.
  243. Scanlan, Christopher M.; Berry, Christopher J., Stackable semiconductor package including laminate interposer.
  244. Huemoeller,Ronald Patrick; Rusli,Sukianto; Hiner,David Jon, Stacked embedded leadframe.
  245. Kim, Yoon Joo; Kim, In Tae; Chung, Ji Young; Kim, Bong Chan; Kim, Do Hyung; Ha, Sung Chul; Lee, Sung Min; Song, Jae Kyu, Stacked semiconductor package and method of making same.
  246. Hsin, Chung Hsien, Stacked structure for an image sensor.
  247. Hsieh, Jackson; Wu, Jichen; Chen, Bruce, Stacked structure of an image sensor.
  248. Andoh, Jun; Tsuyuki, Tatsuya, Supporting structure for a solid state image sensing device.
  249. Miks, Jeffrey Alan; Zwenger, Curtis Michael; Gogue, Brenda, Tape supported memory card leadframe structure.
  250. Miks,Jeffrey A.; Zwenger,Curtis M.; d'Estries,Maximilien; Shermer,Stephen G., Tape supported memory card leadframe structure.
  251. McCann,David R.; Groover,Richard L.; Hoffman,Paul R., Thermally enhanced chip scale lead on chip semiconductor package and method of making same.
  252. McCann,David R.; Groover,Richard L.; Hoffman,Paul R., Thermally enhanced chip scale lead on chip semiconductor package and method of making same.
  253. Chua, Swee Kwang, Thin semiconductor die packages and associated systems and methods.
  254. Dunlap, Brett Arnold; Copia, Alexander William, Thin stackable package and method.
  255. Berry, Christopher J.; Scanlan, Christopher M., Thin stacked interposer package.
  256. Berry, Christopher J.; Scanlan, Christopher M., Thin stacked interposer package.
  257. Hiner, David Jon; Huemoeller, Ronald Patrick, Through via connected backside embedded circuit features structure and method.
  258. Hiner, David Jon; Huemoeller, Ronald Patrick, Through via connected backside embedded circuit features structure and method.
  259. Huemoeller, Ronald Patrick; Reed, Frederick Evans; Hiner, David Jon; Lee, Kiwook, Through via nub reveal method and structure.
  260. Huemoeller, Ronald Patrick; Reed, Frederick Evans; Hiner, David Jon; Lee, Kiwook, Through via nub reveal method and structure.
  261. Hiner, David Jon; Huemoeller, Ronald Patrick; Kelly, Michael G., Through via recessed reveal structure and method.
  262. Hiner, David Jon; Huemoeller, Ronald Patrick; Kelly, Michael G., Through via recessed reveal structure and method.
  263. Huemoeller, Ronald Patrick; Lie, Russ; Hiner, David, Two-sided fan-out wafer escape package.
  264. Huemoeller,Ronald Patrick; Lie,Russ; Hiner,David, Two-sided wafer escape package.
  265. Huemoeller,Ronald Patrick; Lie,Russ; Hiner,David, Two-sided wafer escape package.
  266. Nondhasitthichai, Somchai; Sirinorakul, Saravuth, Very extremely thin semiconductor package.
  267. Nondhasitthichai, Somchai; Sirinorakul, Saravuth, Very extremely thin semiconductor package.
  268. Huemoeller, Ronald Patrick; Rusli, Sukianto; Razu, David, Wafer level package and fabrication method.
  269. Huemoeller, Ronald Patrick; Rusli, Sukianto; Razu, David, Wafer level package and fabrication method.
  270. Huemoeller, Ronald Patrick; Rusli, Sukianto; Razu, David, Wafer level package and fabrication method.
  271. Huemoeller, Ronald Patrick; Rusli, Sukianto; Razu, David, Wafer level package and fabrication method.
  272. Huemoeller, Ronald Patrick; Rusli, Sukianto; Razu, David, Wafer level package and fabrication method.
  273. Huemoeller, Ronald Patrick; Rusli, Sukianto; Razu, David, Wafer level package and fabrication method.
  274. Huemoeller, Ronald Patrick; Rusli, Sukianto; Razu, David, Wafer level package and fabrication method.
  275. Huemoeller, Ronald Patrick; Rusli, Sukianto; Razu, David, Wafer level package and fabrication method.
  276. Huemoeller,Ronald Patrick; Rusli,Sukianto; Razu,David, Wafer level package and fabrication method.
  277. Huemoeller, Ronald Patrick; Rusli, Sukianto; Razu, David, Wafer level package fabrication method.
섹션별 컨텐츠 바로가기

AI-Helper ※ AI-Helper는 오픈소스 모델을 사용합니다.

AI-Helper 아이콘
AI-Helper
안녕하세요, AI-Helper입니다. 좌측 "선택된 텍스트"에서 텍스트를 선택하여 요약, 번역, 용어설명을 실행하세요.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.

선택된 텍스트

맨위로