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Semiconductor device and method of fabricating the same 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-023/48
출원번호 US-0313172 (1999-05-18)
우선권정보 JP-0141481 (1998-05-22)
발명자 / 주소
  • Yanagida, Toshiharu
출원인 / 주소
  • Sony Corporation
대리인 / 주소
    Sonnenschein, Nath & Rosenthal
인용정보 피인용 횟수 : 29  인용 특허 : 23

초록

An adhesion layer made from Al film or Ti film is formed on Cu electrode pad portions as external connection terminals of a Cu interconnection layer of an LSI formed on the surface layer of a semiconductor substrate. A BLM film having a stacked structure of Cr/Cu/Au or Ti/Cu/Au is formed on the adhe

대표청구항

1. A semiconductor device comprising: A semiconductor substrate in contact with a multilayer interconnection layer, said multilayer interconnection layer comprising an electrode pad portion as an external connection terminal of the multilayer interconnection layer, said multilayer interconnection

이 특허에 인용된 특허 (23)

  1. Hwang Lih-Tyng ; Lytle William H., Bonding structure for an electronic device.
  2. Scholz Kenneth D. (4150 Willmar Dr. Palo Alto CA 94306), Compressive bump-and-socket interconnection scheme for integrated circuits.
  3. Bhattacharya Somnath (Wappingers Falls NY), Compressively stresses titanium metallurgy for contacting passivated semiconductor devices.
  4. Akram Salman, Conductive bumps on die for flip chip application.
  5. Shinkawata Hiroki,JPX, DRAM semiconductor device with composite bit line.
  6. Dalal Hormazdyar Minocher ; Fallon Kenneth Michael, Direct chip attach circuit card.
  7. Beddingfield Stanley Craig, Flip chip bump structure and method of making.
  8. Tsukamoto Kenji (Tokyo JPX), Interconnection structure of electronic parts.
  9. Geffken Robert Michael ; Motsiff William Thomas ; Uttecht Ronald R., Personalization structure for semiconductor devices.
  10. Fukasawa Hiroyuki,JPX, Printed wiring board and electronic device using same.
  11. Agarwala Birendra N. (Hopewell Junction NY), Process of making pad structure for solder ball limiting metallurgy having reduced edge stress.
  12. Sahara Kunizo (Tokyo JPX) Otsuka Kanji (Higashiyamato JPX) Ishida Hisashi (Higashiyamato JPX), Semiconductor device and process for producing the same.
  13. Akagawa Masatoshi,JPX ; Higashi Mitsutoshi,JPX ; Iizuka Hajime,JPX ; Arai Takehiko,JPX, Semiconductor device having an element with circuit pattern thereon.
  14. Hiruta Yoichi,JPX, Semiconductor device having ball grid array.
  15. Mori Katsunobu (Nara JPX), Semiconductor device having external electrodes formed in concave portions of an anisotropic conductive film.
  16. Yamamoto Mitsuhiko,JPX, Semiconductor device having interconnect lines and connection electrodes formed in groove portions of an insulating laye.
  17. Kimura Naoto,JPX, Semiconductor device having simple protective structure and process of fabrication thereof.
  18. Baba Mikio,JPX, Semiconductor device mounting structure.
  19. Moriyama Yoshifumi,JPX, Semiconductor device with a solder bump over a pillar form.
  20. Kondo Ichiharu (Nagoya JPX) Noritake Chikage (Ama-gun JPX) Watanabe Yusuke (Obu JPX), Semiconductor device with bump structure.
  21. Yamada Hiroshi,JPX ; Togasaki Takasi,JPX ; Saito Masayuki,JPX ; Honma Soichi,JPX ; Mori Miki,JPX ; Tateyama Kazuki,JPX, Semiconductor device with improved encapsulating resin.
  22. Ono Masahiro,JPX ; Bessho Yoshihiro,JPX, Semiconductor unit with semiconductor device mounted with conductive adhesive.
  23. Schaefer William Jeffrey ; Kao Pai-Hsiang ; Kelkar Nikhil Vishwanath, Surface mount die: wafer level chip-scale package and process for making the same.

이 특허를 인용한 특허 (29)

  1. Philippsen, Bengt; Klammer, Hans-Joerg, Bond pad structure and method for producing same.
  2. Lee, Jin-Yuan; Lo, Hsin-Jung, Chip assembly with interconnection by metal bump.
  3. Cheng, Kangguo; Dalton, Timothy J.; Farooq, Mukta G.; Fitzsimmons, John A.; Hsu, Louis L., Forming semiconductor chip connections.
  4. Hsu, Louis Lu-Chen; Cheng, Kangguo; Dalton, Timothy J.; Farooq, Mukta G.; Fitzsimmons, John A., Forming semiconductor chip connections.
  5. Hsu, Louis Lu-Chen; Cheng, Kangguo; Dalton, Timothy J.; Farooq, Mukta G.; Fitzsimmons, John A., Forming semiconductor chip connections.
  6. Wada, Tamaki; Tobita, Akihiro; Ichihara, Seiichi, Method of manufacturing semiconductor device.
  7. Lin, Mou-Shiung; Lee, Jin-Yuan, Semiconductor chip structure.
  8. Morifuji, Tadahiro; Ueda, Shigeyuki, Semiconductor device.
  9. Morifuji, Tadahiro; Ueda, Shigeyuki, Semiconductor device.
  10. Morifuji, Tadahiro; Ueda, Shigeyuki, Semiconductor device.
  11. Morifuji, Tadahiro; Ueda, Shigeyuki, Semiconductor device.
  12. Morifuji, Tadahiro; Ueda, Shigeyuki, Semiconductor device.
  13. Morifuji, Tadahiro; Ueda, Shigeyuki, Semiconductor device.
  14. Morifuji, Tadahiro; Ueda, Shigeyuki, Semiconductor device.
  15. Takaike, Eiji, Semiconductor device.
  16. Takewaki,Toshiyuki; Oda,Noriaki; Kunimune,Yorinobu, Semiconductor device having an anti-oxidizing layer that inhibits corrosion of an interconnect layer.
  17. Wada, Tamaki; Tobita, Akihiro; Ichihara, Seiichi, Semiconductor device having electrode/film opening edge spacing smaller than bonding pad/electrode edge spacing.
  18. Higuchi, Shingo, Semiconductor device including a protective film.
  19. Higuchi, Shingo, Semiconductor device including a protective film.
  20. Higuchi, Shingo, Semiconductor device including a protective film.
  21. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  22. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  23. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  24. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  25. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  26. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  27. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  28. Lin, Mou-Shiung; Chen, Michael; Chou, Chien-Kang; Chou, Mark, Wirebond pad for semiconductor chip or wafer.
  29. Lin,Mou Shiung; Chen,Michael; Chou,Chien Kang; Chou,Mark, Wirebond pad for semiconductor chip or wafer.
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