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A one transistor, non-volatile programmable switch having four operating states for connection between circuit elements and passive elements including bus lines and input/output pads. The four states include a first unidirectional state in which the cell allows signal flow in a first direction, a se

A one transistor, non-volatile programmable switch having four operating states for connection between circuit elements and passive elements including bus lines and input/output pads. The four states include a first unidirectional state in which the cell allows signal flow in a first direction, a second unidirectional state in which the cell allows signal flow in a second direction, opposite to the first direction, a third state in which the cell allows bi-directional signal flow, and a fourth state resenting high impedance in which signal flow is blocked (the switch is open). A non-volatile programmable transistor having a drain coupled to one of the first node and second node, a source coupled to the other of the first node and second node, a gate coupled to an energizing conductor, and a data storage structure constitute the programmable switch. The non-volatile programmable transistor used in the switch is a charge programmable device (e.g. SONOS cell), in which the data storage structure comprises a nitride layer, or other charge tapping layer, between oxides or other insulators.

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A one transistor, non-volatile programmable switch having four operating states for connection between circuit elements and passive elements including bus lines and input/output pads. The four states include a first unidirectional state in which the cell allows signal flow in a first direction, a se

A one transistor, non-volatile programmable switch having four operating states for connection between circuit elements and passive elements including bus lines and input/output pads. The four states include a first unidirectional state in which the cell allows signal flow in a first direction, a second unidirectional state in which the cell allows signal flow in a second direction, opposite to the first direction, a third state in which the cell allows bi-directional signal flow, and a fourth state resenting high impedance in which signal flow is blocked (the switch is open). A non-volatile programmable transistor having a drain coupled to one of the first node and second node, a source coupled to the other of the first node and second node, a gate coupled to an energizing conductor, and a data storage structure constitute the programmable switch. The non-volatile programmable transistor used in the switch is a charge programmable device (e.g. SONOS cell), in which the data storage structure comprises a nitride layer, or other charge tapping layer, between oxides or other insulators. claim 1, wherein currents through said first and said second current source are made to match by making the channel length of said first and second current source larger than of said first and said second switching means. 3. The circuit of claim 1, wherein for equal drain current, differences in the transconductance gmof said first and said second switching means do not vary by more than 2.5% for a 5% difference in the length of said first and said second switching means. 4. The circuit of claim 1, wherein said switching means of said first conductivity type are substituted by a second conductivity type, where said first and said second conductivity types are opposite conductivity types. 5. A high frequency fixed gain differential metal oxide semiconductor (MOS) amplifier, comprising: a first MOS transistor of a first conductivity type having a first terminal and a second terminal, said first terminal of said first MOS transistor coupled via a first load resistive means to a first power supply, the junction of said first terminal of said first MOS transistor and said first load resistive means providing a first output; said second terminal of said first MOS transistor coupled via a first current source to a second power supply less positive than said first power supply; a second MOS transistor, identical to said first MOS transistor, having a first terminal and a second terminal, said first terminal of said second MOS transistor coupled via a second load resistive means, equal in resistance to said first load resistive means, to said first power supply, the junction of said first terminal of said second MOS transistor and said second load resistive means providing a second output, where said first and said second output provides a fixed gain differential output signal based on a first and a second input signal applied to a first and a second input terminal; said second terminal of said second MOS transistor coupled via a second current source, identical to said first current source, to said second power supply; the gate of said first MOS transistor in communication with said first input terminal; the gate of said second MOS transistor in communication with said second input terminal; frequency compensating means in communication with said second terminal of said first and said second MOS transistor, said frequency compensating means further comprising: a first series resistive means serially coupled to a first capacitive means, where said first series resistive means is coupled to said second terminal of said second MOS transistor, and a plate of said first capacitive means is coupled to said second terminal of said first MOS transistor; and a second series resistive means serially coupled to a second capacitive means, where said second series resistive means is coupled to said second terminal of said first MOS transistor, and a plate of said second capacitive means is coupled to said second terminal of said second MOS transistor; a first parasitic capacitance coupled between said plate of said first capacitive means and said second power supply; and a second parasitic capacitance coupled between said plate of said second capacitive means and said second power supply, said first and said second parasitic capacitance reducing the impedance at the second terminal of said first and said second MOS transistor. 6. The circuit of claim 5, wherein currents through said first and said second current source are made to match by using long channel lengths in said first and second current source. 7. The circuit of claim 5, wherein for equal drain current, differences in the transconductance gmof said first and said second switching means do not vary by more than 2.5% for a 5% difference in the length of said first and said second switching means. 8. The circuit of claim 5, wherein said switching means of said first conductivity type are substituted by a second conductivity type, where said first an d said second conductivity types are opposite conductivity types. 9. The circuit of claim 5, wherein the impedance of said capacitive means is smaller than the impedance of said resistive means at the desired signal frequency. 10. A multistage high frequency fixed gain differential metal oxide semiconductor (MOS) amplifier, comprising: inputs (In1) and (In2) and outputs (Out1) and (Out2), and a first and a second differential amplifier stage, each of said first and second differential amplifier stages having an input (G1) and an input (G2) and outputs node (A) and node (B), where said input (G1) and said input (G2) of said first differential amplifier stage is coupled to said input (In1) and said input (In2), respectively, where said input (G1) and said input (G2) of said second differential amplifier stage is direct-coupled to said node (A) and said node (B) of said first differential amplifier stage, respectively, where said node (A) and said node (B) of said second differential amplifier stage is coupled to said output (Out1) and said output (Out2), respectively, said first and said second differential amplifier stage together providing a fixed gain at said outputs (Out1) and (Out2) based on signals applied to said inputs (In1) and (In2), said first and said second differential amplifier stage each further comprising: a first MOS transistor of a first conductivity type having a first terminal and a second terminal, said first terminal of said first MOS transistor coupled via a first load resistive means to a first power supply, the junction of said first terminal of said first MOS transistor and said first load resistive means labeled node (A); said second terminal of said first MOS transistor coupled via a first current source to a second power supply less positive than said first power supply; a second MOS transistor, identical to said first MOS transistor, having a first terminal and a second terminal, said first terminal of said second MOS transistor coupled via a second load resistive means, equal in resistance to said first load resistive means, to said first power supply, the junction of said first terminal of said second MOS transistor and said second load resistive means labeled node (B), where said node (A) and said node (B) provides a differential output signal based on said inputs (G1) and (G2); said second terminal of said second MOS transistor coupled via a second current source, identical to said first current source, to said second power supply; the gate of said first MOS transistor coupled to said input (G1); the gate of said second MOS transistor coupled to said input (G2); frequency compensating means in communication with said second terminal of said first and said second MOS transistor, said frequency compensating means further comprising: a first series resistive means serially coupled to a first capacitive means, where said first series resistive means is coupled to said second terminal of said second MOS transistor, and a plate of said first capacitive means is coupled to said second terminal of said first MOS transistor; and a second series resistive means serially coupled to a second capacitive means, where said series second resistive means is coupled to said second terminal of said first MOS transistor, and a plate of said second capacitive means is coupled to said second terminal of said second MOS transistor; a first parasitic capacitance coupled between said plate of said first capacitive means and said second power supply; and a second parasitic capacitance coupled between said plate of said second capacitive means and said second power supply, said first and said second parasitic capacitance reducing the impedance at the second terminal of said first and said second MOS transistor. 11. The circuit of claim 10, wherein currents through said first and said second current source are made to match by using long channel lengths in said first and second current source. 12. The circuit of claim 10, wherein for equal drain current, differences in the transconductance gmof said first and said second switching means do not vary by more than 2.5% for a 5% difference in the length of said first and said second switching means. 13. The circuit of claim 10, wherein said switching means of said first conductivity type are substituted by a second conductivity type, where said first and said second conductivity types are opposite conductivity types. 14. The circuit of claim 10, wherein the impedance of said capacitive means is smaller than the impedance of said resistive means at the desired signal frequency. 15. A high frequency variable gain differential metal oxide semiconductor (MOS) amplifier, comprising: a first and a second differential amplifier stage, each having an input (G1) and an input (G2) and outputs node (A) and node (B), said nodes (A) coupled together and said nodes (B) coupled together, where said input (G1) and said input (G2) of said first differential amplifier stage is coupled to an input (In1) and an input (In2), respectively, where said input (G1) and said input (G2) of said second differential amplifier stage is coupled to said input (In2) and said input (In1), respectively, where said node (B) is coupled to an output (Out1) and where said node (A) is coupled to an output (Out2), said first and said second differential amplifier stage together providing a variable gain at said outputs (Out1) and (Out2) based on signals applied to said inputs (In1) and (In2), said first and said second differential amplifier stage each further comprising: a first MOS transistor of a first conductivity type having a first and a second terminal, said first terminal of said first MOS transistor coupled via a first load resistive means to a first power supply, the junction of said first terminal of said first MOS transistor and said first load resistive means labeled node (A); said second terminal of said first MOS transistor coupled via a first current source to a second power supply less positive than said first power supply; a second MOS transistor, identical to said first MOS transistor, having a first and a second terminal, said first terminal of said second MOS transistor coupled via a second load resistive means, equal in resistance to said first load resistive means, to said first power supply, the junction of said first terminal of said second MOS transistor and said second load resistive means labeled node (B), where said node (A) and said node (B) provides a differential output signal based on said inputs (G1) and (G2); said second terminal of said second MOS transistor coupled via a second current source, identical to said first current source, to said second power supply; the gate of said first MOS transistor coupled to said input (G1); the gate of said second MOS transistor coupled to said input (G2); frequency compensating means in communication with said second terminal of said first and said second MOS transistor, said frequency compensating means further comprising: a first series resistive means serially coupled to a first capacitive means, where said first series resistive means is coupled to said second terminal of said second MOS transistor, and a plate of said first capacitive means is coupled to said second terminal of said first MOS transistor; and a second series resistive means serially coupled to a second capacitive means, where said second series resistive means is coupled to said second terminal of said first MOS transistor, and a plate of said second capacitive means is coupled to said second terminal of said second MOS transistor; a first parasitic capacitance coupled between said plate of said first capacitive means and said second power supply; and a second parasitic capacitance coupled between said plate of said second capacitive means and said second power supply, said first and said second parasitic capacitance reducing the impedance at said