초록 ▼

Method and apparatus for efficiently traversing and placing cells in a circuit design database are disclosed. In one illustrative embodiment, one or more leaf cells are identified as base objects. The base objects are placed and aligned along a selected dominate axis. Once the base objects are ident

Method and apparatus for efficiently traversing and placing cells in a circuit design database are disclosed. In one illustrative embodiment, one or more leaf cells are identified as base objects. The base objects are placed and aligned along a selected dominate axis. Once the base objects are identified, an input port is identified by the circuit designer. In many cases, selected base objects will have at least one common input port name, such as "A". By selecting a common input port name, the corresponding input port for each of the selected base objects is identified. Once identified, the source leaf cells that have an output port that is coupled to the identified input ports can be identified, placed and aligned as desired.

대표청구항 ▼

Method and apparatus for efficiently traversing and placing cells in a circuit design database are disclosed. In one illustrative embodiment, one or more leaf cells are identified as base objects. The base objects are placed and aligned along a selected dominate axis. Once the base objects are ident

Method and apparatus for efficiently traversing and placing cells in a circuit design database are disclosed. In one illustrative embodiment, one or more leaf cells are identified as base objects. The base objects are placed and aligned along a selected dominate axis. Once the base objects are identified, an input port is identified by the circuit designer. In many cases, selected base objects will have at least one common input port name, such as "A". By selecting a common input port name, the corresponding input port for each of the selected base objects is identified. Once identified, the source leaf cells that have an output port that is coupled to the identified input ports can be identified, placed and aligned as desired. ast one course delay element drives the data path independent of the operation of a test path. 11. The circuitry as recited in claim 1, wherein one of said plurality of inverters in said fine delay element and said at least one course delay element connects a test path, wherein said test path is used to detect faults at said fine delay element and said at least one course delay element. 12. Circuitry in an integrated circuit for linearly delaying a signal comprising: a plurality of control signals; a fine delay element coupled to at least one of said plurality of control signals, wherein said fine delay element comprises logic circuitry configured to provide fine adjustments to the delay of said signal, at least one course delay element coupled to said fine delay element, wherein said at least one course delay element is coupled to at least one of said plurality of control signals, wherein said at least one course delay element comprises logic circuitry configured to provide course adjustments to the delay of said signal; wherein said fine delay element and said at least one course delay element are configured to provide linear delay steps; and wherein said fine delay element and said at least one course delay element comprise a plurality of selectable propagation paths, wherein said plurality of selectable propagation paths are linear in delay with respect to one another. 13. Circuitry in an integrated circuit for linearly delaying a signal comprising: a plurality of control signals; a fine delay element coupled to at least one of said plurality of control signals, wherein said fine delay element comprises logic circuitry configured to provide fine adjustments to the delay of said signal, at least one course delay element coupled to said fine delay element, wherein said at least one course delay element is coupled to at least one of said plurality of control signals, wherein said at least one course delay element comprises logic circuitry configured to provide course adjustments to the delay of said signal; wherein said file delay element and said at least one course delay element are configured to provide linear delay steps; and wherein said fine delay element and said at least one course delay element are coupled in a manner where a signal propagates from said fine delay element to said at least one course delay element and back to said fine delay element. 14. Circuitry in an integrated circuit for linearly delaying a signal comprising: a plurality of control signals; a fine delay element coupled to at least one of said plurality of control signals, wherein said fine delay element comprises logic circuitry configured to provide fine adjustments to the delay of said signal, at least one course delay element coupled to said fine delay element, wherein said at least one course delay element is coupled to at least one of said plurality of control signals, wherein said at least one course delay element comprises logic circuitry configured to provide course adjustments to the delay of said signal; wherein said fine delay element and said at least one course delay element are configured to provide linear delay steps; and wherein a test signal is coupled to said fine delay element and to each of said at least one course delay element, wherein said test signal is used to detects faults at said fine delay element and each of said at least one course delay element. 15. The circuitry as recited in claim 14, wherein said logic circuitry of said fine delay element and said at least one course delay element each comprise a plurality of transmission gates, a plurality of inverters, at least one dummy load and at least one logic gate. 16. The circuitry as recited in claim 15, wherein said at least one logic gate in said fine delay element and said at least one course delay element receives said test signal. 17. The circuitry as recited in claim 15, wherein a particular inverter of one of said plurality of inverter s of said fine delay element and said at least one course delay element drives the data path in functional mode, wherein said test signal is deasserted during functional mode, wherein a test path is disconnected during functional mode, wherein by disconnecting said test path during functional mode power is reduced. 18. The circuitry as recited in claim 14, wherein each of said at least one course delay element comprises: an input coupled to a first and a second transmission gate; a third transmission gate coupled to said first transmission gate; a first and second inverter coupled to said second transmission gate; a third and fourth inverter coupled to said first transmission gate, wherein said third inverter connects a test path, wherein said fourth inverter drives a data path; a fourth transmission gate coupled to said fourth inverter; an output to a prior delay element coupled to said fourth inverter; a fifth inverter coupled to said third transmission gate; and a first logic gate coupled to receive said test signal, wherein an output of said logic gate is coupled to said fourth transmission gate. 19. The circuitry as recited in claim 14, wherein said fine delay element comprises: a first, a second and a third inverter coupled to receive an input signal; a first transmission gate coupled to said first inverter; a second transmission gate coupled to said second inverter; a fourth, a fifth and a sixth inverter coupled to said third inverter; a third and fourth transmission gate coupled to said fourth inverter; a seventh inverter coupled to said third and fourth transmission gate; a fifth and a sixth transmission gate coupled to said first and second transmission gate; a seventh and an eighth transmission gate coupled to said seventh inverter; an eighth inverter coupled to said fifth transmission gate, wherein said eighth inverter drives a data path; an output coupled to said eighth inverter; a ninth transmission gate coupled to said eighth inverter, wherein said ninth transmission gate is coupled to receive said input signal from a subsequent delay element; a ninth inverter coupled to said sixth and eighth transmission gate, wherein said ninth inverter outputs said input signal to said subsequent delay element; a tenth transmission gate coupled to said output; a tenth inverter coupled to said tenth transmission gate; an eleventh inverter coupled to said ninth transmission gate; a twelfth inverter coupled to said eighth inverter, wherein said twelfth inverter connects a test path; and a first logic gate coupled to receive said test signal, wherein an output of said logic gate is coupled to said tenth transmission gate. 20. Circuitry in an integrated circuit for linearly delaying a signal comprising: a plurality of control signals; a fine delay element coupled to at least one of said plurality of control signals, wherein said fine delay element comprises logic circuitry configured to provide fine adjustments to the delay of said signal, at least one course delay element coupled to said fine delay element, wherein said at least one course delay element is coupled to at least one of said plurality of control signals, wherein said at least one course delay element comprises logic circuitry configured to provide course adjustments to the delay of said signal; wherein said fine delay element and said at least one course delay element are configured to provide linear delay steps; and wherein each of said at least one course delay element comprises: an input coupled to a first and a second transmission gate; a third transmission gate coupled to said first transmission gate; a first and second inverter coupled to said second transmission gate; a third and fourth inverter coupled to said first transmission gate, wherein said third inverter connects a test path, wherein said fourth inverter drives a data path; a fourth transmission gate coupled to said third inverter; an output to a prior de lay element coupled to said fourth inverter; and a fifth inverter coupled to said fourth transmission gate. 21. Circuitry in an integrated circuit for linearly delaying a signal comprising: a plurality of control signals; a fine delay element coupled to at least one of said plurality of control signals, wherein said fine delay element comprises logic circuitry configured to provide fine adjustments to the delay of said signal, at least one course delay element coupled to said fine delay element, wherein said at least one course delay element is coupled to at least one of said plurality of control signals, wherein said at least one course delay element comprises logic circuitry configured to provide course adjustments to the delay of said signal; wherein said fine delay element and said at least one course delay element are configured to provide linear delay steps; and wherein said fine delay element comprises: a first, a second and a third inverter coupled to receive an input signal; a first transmission gate coupled to said first inverter; a second transmission gate coupled to said second inverter; a fourth, a fifth and a sixth inverter coupled to said third inverter; a third and fourth transmission gate coupled to said fourth inverter; a seventh inverter coupled to said third and fourth transmission gate; a fifth and a sixth transmission gate coupled to said first and second transmission gate; a seventh and an eighth transmission gate coupled to said seventh inverter; an eighth inverter coupled to said fifth transmission gate, wherein said eighth inverter drives a data path; an output coupled to said eighth inserter; a ninth transmission gate coupled to said eighth inverter, wherein said ninth transmission gate is coupled to receive said input signal from a subsequent delay element; a ninth inverter coupled to said sixth and eighth transmission gate, wherein said ninth inverter outputs said input signal to said subsequent delay element; a tenth transmission gate coupled to said output; a tenth inverter coupled to said tenth transmission gate; an eleventh inverter coupled to said ninth transmission gate; and a twelfth inverter coupled to said eighth inverter, wherein said twelfth inverter connects a test path. 22. A method for linearly delaying a signal in an integrated circuit comprising the steps of: receiving a plurality of control signals; providing fine adjustments to the delay of said signal in a fine delay element coupled to at least one of said plurality of control signals, wherein said fine delay element comprises logic circuitry configured to provide fine adjustments to the delay of said signal; providing course adjustments to the delay of said signal in at least one course delay element coupled to at least one of said plurality of control signals, wherein said at least one course delay element comprises logic circuitry configured to provide course adjustments to the delay of said signal, wherein said at least one course delay element is coupled to said fine delay element; wherein said fine delay element and said at least one course delay element are configured to provide linear delay steps; and wherein said logic circuitry of said fine delay element and said at least one course delay element each comprise a plurality of transmission gates, a plurality of inverters and at least one dummy load. 23. The method as recited in claim 22, wherein said linear delay steps are adjusted by adjusting the size of at least one channel width of at least one particular inverter of said plurality of inverters of said fine delay element. 24. The method as recited in claim 23, wherein said adjusting the size of at least one channel width of at least one particular inverter of said plurality of inverters of said fine delay element is accomplished without affecting the driveability of the data path. 25. The method as recited in claim 22, wherein said linear delay steps are adjusted by adjusting th