IPC분류정보
국가/구분 |
United States(US) Patent
등록
|
국제특허분류(IPC7판) |
|
출원번호 |
US-0449098
(1999-11-24)
|
발명자
/ 주소 |
- Van Doorn, Leendert Peter
|
출원인 / 주소 |
- International Business Machines Corporation
|
대리인 / 주소 |
|
인용정보 |
피인용 횟수 :
152 인용 특허 :
10 |
초록
▼
The Virtual Machine is viewed by many as inherently insecure despite all the efforts to improve its security. This invention provides methods, apparatus, and computer products to implement a system that provides operating system style protection for code. Although applicable to many language systems
The Virtual Machine is viewed by many as inherently insecure despite all the efforts to improve its security. This invention provides methods, apparatus, and computer products to implement a system that provides operating system style protection for code. Although applicable to many language systems, the invention is described for a system employing the Java language. Hardware protection domains are used to separate Java classes, provide access control on cross domain method invocations, efficient data sharing between protection domains, and memory and CPU resource control. Apart from the performance impact, these security measures are all transparent to the Java programs, even when a subclass is in one domain and its superclass is in another, when they do not violate the policy. To reduce the performance impact, classes are grouped and shared between protection domains and map data lazily as it is being shared. The system has been implemented on top of the Paramecium operating system used as an example of an extensible operating system application.
대표청구항
▼
The Virtual Machine is viewed by many as inherently insecure despite all the efforts to improve its security. This invention provides methods, apparatus, and computer products to implement a system that provides operating system style protection for code. Although applicable to many language systems
The Virtual Machine is viewed by many as inherently insecure despite all the efforts to improve its security. This invention provides methods, apparatus, and computer products to implement a system that provides operating system style protection for code. Although applicable to many language systems, the invention is described for a system employing the Java language. Hardware protection domains are used to separate Java classes, provide access control on cross domain method invocations, efficient data sharing between protection domains, and memory and CPU resource control. Apart from the performance impact, these security measures are all transparent to the Java programs, even when a subclass is in one domain and its superclass is in another, when they do not violate the policy. To reduce the performance impact, classes are grouped and shared between protection domains and map data lazily as it is being shared. The system has been implemented on top of the Paramecium operating system used as an example of an extensible operating system application. -6058252, 20000500, Noll et al., 716/010; US-6209123, 20010300, Maziasz et al., 716/011; US-6308309, 20011000, Gan et al., 326/039 he selected portion being heated, a state-changing transition between a failed mode and a recovered mode in the suspect signal path site; and using the detected state-changing transition, determining that the signal path site has a resistivity that changes between the failed mode and the recovered mode. 9. The method of claim 8 wherein said step of detecting includes determining that said trigger signal has said second value. 10. The method of claim 1 wherein said trigger signal is operable for correlating a failure of said pattern under test and a structural portion of said DUT. 11. A computer program product embodied in a tangible storage medium, said program product including a program of instructions for performing the steps of: sequentially driving a first set of pattern vectors on a device under test (DUT), wherein a first predetermined vector of said first set of pattern vectors comprises a pattern vector under test, and outputting a trigger signal having a first value in association with said sequentially driving said first set of pattern vectors; if a pattern vector other than said first predetermined vector fails, sequentially driving a second set of pattern vectors on said DUT, wherein a second predetermined vector of said second set of pattern vectors comprises said pattern vector under test, and outputting said trigger signal having a second value in association said sequentially driving said second set of pattern vectors. 12. The program product of claim 11 further including instructions for performing the step of, if said first predetermined vector fails, repeating said step of sequentially driving said first set of pattern vectors on said DUT. 13. The program product of claim 11 further including instructions for performing the steps of, if no pattern vector fails: repeating said step of sequentially driving said second set of pattern vectors on said DUT and outputting said trigger signal having said second value in association with said sequentially driving said second set of pattern vectors; and varying a device parameter of said DUT until at least one of said second set of pattern vector fails. 14. The program product of claim 13 wherein said step of varying said device parameter comprises the step of raising a temperature of said DUT. 15. The program product of claim 11 further including programming for performing the steps of: if said second predetermined pattern vector fails, repeating said step of sequentially driving said first set of pattern vectors on said DUT and outputting said trigger signal having said first value in association with said sequentially driving said first set of pattern vectors. 16. The program product of claim 15 further including instructions for performing the steps of, if said second predetermined pattern vector does not fail, repeating sequentially driving said second set of pattern vectors on said DUT, and outputting said trigger signal having a second value in association said sequentially driving said second set of pattern vectors; and varying a device parameter of said DUT until at least one of said second set of pattern vector fails. 17. The program product of claim 16 wherein said step of varying said device parameter comprises the step of raising a temperature of said DUT. 18. The program product of claim 11 wherein said trigger signal is operable for correlating a failure of said pattern under test and a structural portion of said DUT. 19. A data processing system comprising: circuitry operable for sequentially driving a first set of pattern vectors on a device under test (DUT), wherein a first predetermined vector of said first set of pattern vectors comprises a pattern vector under test, and outputting a trigger signal having a first value in association with said sequentially driving said first set of pattern vectors; circuitry operable for, if a pattern vector other than said first predetermined vector fails, sequentially driving a secon d set of pattern vectors on said DUT, wherein a second predetermined vector of said second set of pattern vectors comprises said pattern vector under test, and outputting said trigger signal having a second value in association said sequentially driving said second set of pattern vectors. 20. The data processing system of claim 19 further including circuitry operable for, if said first predetermined vector fails, repeating said step of sequentially driving said first set of pattern vectors on said DUT. 21. The data processing system of claim 19 further including circuitry operable for, if no pattern vector fails: repeating said step of sequentially driving said second set of pattern vectors on said DUT and outputting said trigger signal having said second value in association with said sequentially driving said second set of pattern vectors; and varying a device parameter of said DUT until at least one of said second set of pattern vector fails. 22. The data processing system of claim 21 wherein said step of varying said device parameter comprises the step of raising a temperature of said DUT. 23. The data processing system of claim 19 further including: circuitry operable for, if said second predetermined pattern vector fails, repeating said step of sequentially driving said first set of pattern vectors on said DUT and outputting said trigger signal having said first value in association with said sequentially driving said first set of pattern vectors. 24. The data processing system of claim 23 further including: circuitry operable for, if said second predetermined pattern vector does not fail, repeating sequentially driving said second set of pattern vectors on said DUT, and outputting said trigger signal having a second value in association said sequentially driving said second set of pattern vectors; and circuitry operable for varying a device parameter of said DUT until at least one of said second set of pattern vector fails. 25. The data processing system of claim 24 wherein said step of varying said device parameter comprises the step of raising a temperature of said DUT. 26. The data processing system of claim 19 wherein said trigger signal is operable for correlating a failure of said pattern under test and a structural portion of said DUT.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.