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A dual damascene technique that forms a complete via in a single step. Specifically, the method deposits a first insulator layer upon a substrate, an etch stop layer over the first insulator layer, and a second insulator layer atop the etch stop layer. A via mask is then formed by applying a photore

A dual damascene technique that forms a complete via in a single step. Specifically, the method deposits a first insulator layer upon a substrate, an etch stop layer over the first insulator layer, and a second insulator layer atop the etch stop layer. A via mask is then formed by applying a photoresist which is developed and patterned according to the locations of the dimensions of the ultimate via or vias. Thereafter, the first insulator layer, the etch stop layer and the second insulator layer may be etched in a single step, for example, using a reactive ion etch. The hole that is formed through these three layers has the diameter of the ultimate via. Thereafter, a trench is masked and etched into the second insulator layer. The trench etch is stopped by the etch stop layer. The via and trench are metallized to form an interconnect structure. The technique can be repeated to create a multi-level interconnect structure.

대표청구항 ▼

A dual damascene technique that forms a complete via in a single step. Specifically, the method deposits a first insulator layer upon a substrate, an etch stop layer over the first insulator layer, and a second insulator layer atop the etch stop layer. A via mask is then formed by applying a photore

A dual damascene technique that forms a complete via in a single step. Specifically, the method deposits a first insulator layer upon a substrate, an etch stop layer over the first insulator layer, and a second insulator layer atop the etch stop layer. A via mask is then formed by applying a photoresist which is developed and patterned according to the locations of the dimensions of the ultimate via or vias. Thereafter, the first insulator layer, the etch stop layer and the second insulator layer may be etched in a single step, for example, using a reactive ion etch. The hole that is formed through these three layers has the diameter of the ultimate via. Thereafter, a trench is masked and etched into the second insulator layer. The trench etch is stopped by the etch stop layer. The via and trench are metallized to form an interconnect structure. The technique can be repeated to create a multi-level interconnect structure. te conducting structure. 8. The method according to claim 7, wherein the step (e) fills the first interconnection contact hole and the second interconnection contact hole with the second conductive layer to serve as a first interconnection contact plug and a second interconnection contact plug. 9. The method according to claim 1, wherein the substrate comprises a first shallow trench isolation (STI) region between the first gate conducting structure and the second gate conducting structure, and a second STI region between the third gate conducting structure and the fourth gate conducting structure, wherein the first STI region and the second STI region defines the active area. 10. The method according to claim 1, wherein before the step (b) of providing the first conductive layer, the method further comprises the steps of: forming a liner on the entire surface of the substrate; removing the liner disposed on the top of the second gate conducting structure and the third gate conducting structure and the liner disposed on the substrate between the second gate conducting structure and the third gate conducting structure; and filling the gap between the second gate conducting structure and the third gate conducting structure with a first conductive layer. 11. The method according to claim 10, wherein the material used to form the liner is selected from the group consisting of SiN, SiON and silicon oxide.