IPC분류정보
국가/구분 |
United States(US) Patent
등록
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국제특허분류(IPC7판) |
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출원번호 |
US-0042399
(2002-01-08)
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발명자
/ 주소 |
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출원인 / 주소 |
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대리인 / 주소 |
Antonelli, Terry, Stout & Kraus, LLP
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인용정보 |
피인용 횟수 :
7 인용 특허 :
7 |
초록
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Disclosed are a packaging component for packaging a microelectronic (e.g., III-V semiconductor) device, the packaged microelectronic device, and methods for manufacture thereof. The component has sequentially deposited layers of metal (37, 50), to be located within the package, to act as a hydrogen
Disclosed are a packaging component for packaging a microelectronic (e.g., III-V semiconductor) device, the packaged microelectronic device, and methods for manufacture thereof. The component has sequentially deposited layers of metal (37, 50), to be located within the package, to act as a hydrogen getter. The sequentially deposited layers of metal include at least a first layer (3) of Ni adjacent the housing member surface, to improve adherence of the sequentially deposited layers and interstitially trap hydrogen; an outermost layer (11) of palladium to convert molecular hydrogen to hydrogen atoms and to absorb hydrogen; and a layer (9) of Ti or Zr adjacent this outermost layer. Additional layers (5, 7) of nickel and of titanium or zirconium can be provided between the first layer and the layer adjacent the outermost layer. Desirably, the surface of the housing member is roughened prior to depositing the first layer thereon.
대표청구항
▼
Disclosed are a packaging component for packaging a microelectronic (e.g., III-V semiconductor) device, the packaged microelectronic device, and methods for manufacture thereof. The component has sequentially deposited layers of metal (37, 50), to be located within the package, to act as a hydrogen
Disclosed are a packaging component for packaging a microelectronic (e.g., III-V semiconductor) device, the packaged microelectronic device, and methods for manufacture thereof. The component has sequentially deposited layers of metal (37, 50), to be located within the package, to act as a hydrogen getter. The sequentially deposited layers of metal include at least a first layer (3) of Ni adjacent the housing member surface, to improve adherence of the sequentially deposited layers and interstitially trap hydrogen; an outermost layer (11) of palladium to convert molecular hydrogen to hydrogen atoms and to absorb hydrogen; and a layer (9) of Ti or Zr adjacent this outermost layer. Additional layers (5, 7) of nickel and of titanium or zirconium can be provided between the first layer and the layer adjacent the outermost layer. Desirably, the surface of the housing member is roughened prior to depositing the first layer thereon. drain extended transistor of claim 1 wherein a shallow trench isolation region, contained in said second well region, is adjacent to said transistor drain region and is positioned between said transistor drain region of a second conductivity type and said transistor gate. 3. The integrated circuit drain extended transistor of claim 2 further comprising a third well region which contains said second well region. 4. The integrated circuit drain extended transistor of claim 1 wherein said transistor gate comprises: a dielectric layer; and a polysilicon layer overlying said dielectric layer. 5. The integrated circuit drain extended transistor of claim 1 wherein said first conductivity type is p-type and said second conductivity type is n-type. 6. The integrated circuit drain extended transistor of claim 1 wherein said first conductivity type is n-type and said second conductivity type is p-type. 7. The integrated circuit drain extended transistor of claim 1 further comprising a lightly doped region of a second conductivity type contained in said first well region, positioned adjacent to said transistor source region, and partially underlying said transistor gate. 8. An integrated circuit drain extended transistor comprising: a semiconductor substrate comprising a first p-type compensated well region contained in a core CMOS n-well region wherein said first p-type compensated well region comprises a core CMOS n-well implant and a core CMOS p-well implant; a transistor gate partially overlying said first p-type compensated well region and said core CMOS n-well region; a p-type transistor source region adjacent to said transistor gate and contained in said core CMOS n-well region; and a p-type transistor drain region contained in said p-type compensated well region. 9. The integrated circuit drain extended transistor of claim 8 further comprising a p-type transistor lightly doped region contained in said core CMOS n-well region, adjacent to said p-type transistor source region, and extending under a region of said transistor gate. 10. The integrated circuit drain extended transistor of claim 8 further comprising a shallow trench isolation region, contained in said p-type compensated well region, adjacent to said p-type transistor drain region and positioned between said p-type transistor drain region and said p-type transistor source region. 11. An integrated circuit drain extended transistor comprising: a semiconductor substrate comprising a first well region of a first conductivity type adjacent to a second well region of a second conductivity type wherein said first well region is separated from said second well region by a spacing distance; a transistor gate partially overlapping said first well region and said second well region; a transistor source region of a second conductivity type adjacent to said transistor gate and contained in said first well region; and a transistor drain region of a second conductivity type contained in said second well region. 12. The integrated circuit drain extended transistor of claim 11 wherein a shallow trench isolation region, contained in said second well region, is adjacent to said transistor drain region and is positioned between said transistor drain region of a second conductivity type and said transistor gate. 13. The integrated circuit drain extended transistor of claim 12 further comprising a third well region of a first conductivity type that contains said second well region. 14. The integrated circuit drain extended transistor of claim 11 wherein a silicide block structure partially overlies said transistor gate and said second well region and said transistor drain region is positioned adjacent to said silicide block structure. 15. The integrated circuit drain extended transistor of claim 11 wherein said transistor gate comprises: a dielectric layer; and a polysilicon layer overlying said dielectric layer. 16. The integrated circuit drain extended transistor of claim 11 wherein said first conductivity type is n-type and said second conductivity type is p-type. 17. The integrated circuit drain extended transistor of claim 11 wherein said first conductivity type is p-type and said second conductivity type is n-type. 18. The integrated circuit drain extended transistor of claim 11 further comprising a transistor lightly doped region of a second conductivity type contained in said first well region, positioned adjacent to said transistor source region, and partially underlying said transistor gate. 19. The integrated circuit drain extended transistor of claim 18 wherein said second conductivity type is p-type and said first conductivity type is n-type. 20. The integrated circuit drain extended transistor of claim 11 further comprising a third well region of a first conductivity type that contains said second well region. 21. An integrated circuit drain extended transistor comprising: a semiconductor substrate containing a first well region; a transistor gate partially overlapping said first well region; a silicide block structure partially overlapping said transistor gate and said first well region; and a transistor drain region contained in said first well region and positioned adjacent to said silicide block structure. 22. The integrated circuit drain extended transistor of claim 21 further comprising a second well region adjacent to said first well region wherein said transistor gate partially overlaps said second well region. 23. The integrated circuit drain extended transistor of claim 21 wherein said first well region is a CMOS n-well. 24. The integrated circuit drain extended transistor of claim 23 wherein said second well region is a CMOS p-well region. 25. The integrated circuit drain extended transistor of claim 21 wherein said first well region is a CMOS p-well. 26. The integrated circuit drain extended transistor of claim 25 wherein said second well region is a CMOS p-well region. 27. The integrated circuit drain extended transistor of claim 26 further comprising a deep p-well region which contains said first well, region. 28. A drain extended transistor comprising: a semiconductor substrate comprising a first well region of a first conductivity type adjacent to a second well region of a second conductivity type; a transistor gate partially overlapping said first well region and said second well region; a transistor source region of a second conductivity type adjacent to said transistor gate and contained in said first well region; a lightly doped region of a second conductivity type contained in said first well region, adjacent to said transistor source region, and underlying a portion of said transistor gate; and a transistor drain region of a second conductivity type contained in said second well region. 29. The drain extended transistor of claim 28 further comprising a shallow trench isolation region contained in said second well region and positioned between said transistor gate and said transistor drain region. 30. The drain extended transistor of claim 29 further comprising a third well region that contains said second well region. 31. An integrated circuit drain extended transistor comprising: a semiconductor substrate comprising a first n-type compensated well region contained in a core CMOS p-well region wherein said first n-type compensated well region comprises a core CMOS p-well implant and a core CMOS n-well implant; a transistor gate partially overlying said first n-type compensated well region and said core CMOS p-well region; a p-type transistor source region adjacent to said transistor gate and contained in said core CMOS p-well region; and a n-type transistor drain region contained in said n-type compensated well region. 32. The integrated circuit drain extended transistor of claim 31 further comprising a n-type transistor lightly doped region contained in said core CMOS p-well region positioned adjacent to said n-type transisto r source region, and extending under a region of said transistor gate.
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