IPC분류정보
국가/구분 |
United States(US) Patent
등록
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국제특허분류(IPC7판) |
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출원번호 |
US-0592458
(2000-06-09)
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우선권정보 |
JP-0171681 (1999-06-17) |
발명자
/ 주소 |
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출원인 / 주소 |
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대리인 / 주소 |
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인용정보 |
피인용 횟수 :
12 인용 특허 :
7 |
초록
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An information processing device creates a dirty bit indicative of an update state for each combination of sharing bags between parties. A database processing section updates the dirty bit of a tip by monitoring any modification to the tip during a non-synchronous period. A synchronous process is ca
An information processing device creates a dirty bit indicative of an update state for each combination of sharing bags between parties. A database processing section updates the dirty bit of a tip by monitoring any modification to the tip during a non-synchronous period. A synchronous process is carried out between two information processing devices, in which whether it is required to transfer the tip and transfer direction are decided after transfer of the dirty bit. Further, the dirty bit which relates to the synchronous process is updated and the update is transferred to the other dirty bit which corresponds to the tip. As a result, it is possible to reduce communication data volume and to find a coincidence in tips between three or more information processing devices, thereby realizing a database managing device which can reduce communication data volume in the synchronous process in a database system in which associating data can be independently updated by a plurality of devices.
대표청구항
▼
An information processing device creates a dirty bit indicative of an update state for each combination of sharing bags between parties. A database processing section updates the dirty bit of a tip by monitoring any modification to the tip during a non-synchronous period. A synchronous process is ca
An information processing device creates a dirty bit indicative of an update state for each combination of sharing bags between parties. A database processing section updates the dirty bit of a tip by monitoring any modification to the tip during a non-synchronous period. A synchronous process is carried out between two information processing devices, in which whether it is required to transfer the tip and transfer direction are decided after transfer of the dirty bit. Further, the dirty bit which relates to the synchronous process is updated and the update is transferred to the other dirty bit which corresponds to the tip. As a result, it is possible to reduce communication data volume and to find a coincidence in tips between three or more information processing devices, thereby realizing a database managing device which can reduce communication data volume in the synchronous process in a database system in which associating data can be independently updated by a plurality of devices. z et al.; US-6014644, 20000100, Erickson; US-6026087, 20000200, Mirashrafi et al.; US-6026148, 20000200, Dworkin et al.; US-6026400, 20000200, Suzuki; US-6029141, 20000200, Bezos et al.; US-6035021, 20000300, Katz; US-6046762, 20000400, Sonesh et al.; US-6055513, 20000400, Katz et al.; US-6058379, 20000500, Odom et al.; US-6064978, 20000500, Gardner et al.; US-6130933, 20001000, Miloslavsky; US-6175619, 20010100, DeSimone; US-6185194, 20010200, Musk et al.; US-6188673, 20010200, Bauer et al.; US-6192050, 20010200, Stovall; US-6223165, 20010400, Lauffer; US-6230287, 20010500, Pinard et al., 379/265.09; US-6259774, 20010700, Miloslavsky et al. ocessing resource; and (ii) receive said start enable indications from all of said processing modules and in response enable said at least one of said processing modules to generate the start indication for said shared processing resource. 2. A system as defined in claim 1 in which each said processing module that receives a synchronization barrier lock is configured to return said synchronization barrier lock to said synchronization control module, said synchronization control module being configured to increment a synchronization lock counter when it provides a lock to one of said processing modules and to decrement the synchronization lock counter when the synchronization barrier lock is returned. 3. A system as defined in claim 2 in which each processing module is configured to issue a synchronization indication and pause its processing operations prior to issuing a start enable indication. 4. A system as defined in claim 3 in which each processing module that is to provide input data is configured to issue a synchronization call after returning the respective synchronization barrier lock provided thereto. 5. A system as defined in claim 3 in which said synchronization control module is further configured to enable said processing modules to resume their respective processing operations after all of said processing modules have issued their respective synchronization indications. 6. A system as defined in claim 5 in which said synchronization control module is configured to: (A) in response to received a start enable indication from a first of said processing modules, enable said first of said processing modules to pause its processing operations; (B) after receiving start enable indications from others of said processing modules, enabling the first of said processing modules to resume its processing operations and provide a start indication to said shared processing resource. 7. A system as defined in claim 6 in which each processing module is further configured to, after generating their respective start enable indications, generates a wait indication and pauses execution, the synchronization control module being configured to enable the processing modules to resume processing operation after all of them have generated their respective wait indications. 8. A computer program product for controlling a computer in processing of a shared processing resource module, a plurality of processing modules and a synchronization control module, the computer program product comprising a computer readable medium having encoded thereon: A. the shared processing resource module configured to enable the computer to, in response to a start indication, perform processing operations in connection with input data provided by the processing modules; B. each of the plurality of processing modules being configured to enable the computer to perform selected processing operations, at least one of said processing modules also being configured to enable the computer to provide input data to the shared processing resource, each processing module that enables the computer to provide input data being configured to enable the computer to generate a hold indication and provide the input data to the shared processing resource in response to a synchronization barrier lock provided thereto, each processing module further being configured to enable the computer to generate a start enable indication, with each processing module that enables the computer to provide input data being configured to enable the computer to generate the start enable indication after providing the input data, at least one of said processing modules further being configured to enable the computer to generate said start indication for said shared processing resource; and C. said synchronization control module being configured to enable the computer to (i) provide, in response to each hold indication from one of said processing modules, the synchronization barrier lock for enabling said one of said processing modules to, in turn, enable the computer to provide input data to said shared processing resource; and (ii) receive said start enable indications from all of said processing modules and in response enable said at least one of said processing modules to, in turn, enable the computer to generate the start indication for said shared processing resource. 9. A computer program product as defined in claim 8 in which each said processing module that receives a synchronization barrier lock is configured to enable the computer to return said synchronization barrier lock to said synchronization control module, said synchronization control module being configured to enable the computer to increment a synchronization lock counter when it provides a lock to one of said processing modules and to decrement the synchronization lock counter when the synchronization barrier lock is returned. 10. A computer program product as defined in claim 9 in which each processing module is configured to enable the computer to issue a synchronization indication and pause processing operations in connection with the respective processing module prior to issuing a start enable indication. 11. A computer program product as defined in claim 10 in which each processing module that is to enable the computer to provide input data is configured to enable the computer to issue a synchronization call after returning the respective synchronization barrier lock provided thereto. 12. A computer program product as defined in claim 10 in which said synchronization control module is further configured to enable the computer to, in turn, resume processing operations in connection with said processing modules after all of said processing modules have issued their respective synchronization indications. 13. A computer program product as defined in claim 12 in which said synchronization control module is configured to enable the computer to: A) in response to received a start enable indication during processing of a first of said processing modules, enable said computer to pause processing in connection with said first of said processing modules; and (B) after receiving start enable indications from others of said processing modules, enable the computer to resume processing in connection with said first of said processing modules and provide a start indication to said shared processing resource. 14. A computer program product as defined in claim 13 in which each processing module is further configured to, after enabling said computer to generate respective start enable indications in connection therewith, enable the computer to generate a wait indication and pauses execution, the synchronization control module being configured to enable the computer to, in turn, resume processing in connection with all of the processing modules after respective wait indications have been generated in connection therewith. 15. A method for controlling a computer in processing of a shared processing resource module, a plurality of processing modules and a synchronization control module, the method comprising the steps of A. enabling the computer to, in response to a start indication, process said shared processing resource module to perform processing operations in connection with input data provided by the processing modules; B. enabling the computer to process each of the plurality of processing modules to perform selected processing operation, at least one of said processing modules being configured to enable the computer to provide input data to the shared processing resource, each processing module that enables the computer to provide input data being configured to enable the computer to generate a hold indication and provide the input data to the shared processing resource module in response to a synchronization barrier lock provided thereto, each processing module further being configured to enable the computer to generate a start en able indication, with each processing module that enables the computer to provide input data being configured to enable the computer to generate the start enable indication after providing the input data, at least one of said processing modules further being configured to enable the computer to generate said start indication for said shared processing resource; and C. enabling the computer to process said synchronization control module to (i) provide, in response to each hold indication from one of said processing modules, the synchronization barrier lock for enabling said one of said processing modules to, in turn, enable the computer to provide input data to said shared processing resource; and (ii) receive said start enable indications form all of said processing modules and in response enable said at least one of said processing modules to, in turn, enable the computer to generate the start indication for said shared processing resource. 16. A method as defined in claim 15 in which each said processing module that receives a synchronization barrier lock is configured to enable the computer to return said synchronization barrier lock to said synchronization control module, said synchronization control module being configured to enable the computer to increment a synchronization lock counter when it provides a lock to one of said processing modules and to decrement the synchronization lock counter when the synchronization barrier lock is returned. 17. A method as defined in claim 16 in which each processing module is configured to enable the computer to issue a synchronization indication and pause processing operations in connection with the respective processing module prior to issuing a start enable indication. 18. A method as defined in claim 17 in which each processing module that is to enable the computer to provide input data is configured to enable the computer to issue a synchronization call after returning the respective synchronization barrier lock provided thereto. 19. A method as defined in claim 17 in which said synchronization control module is further configured to enable the computer to, in turn, resume processing operations in connection with said processing modules after all of said processing modules have issued their respective synchronization indications. 20. A method as defined in claim 19 in which said synchronization control module is configured to enable the computer to: (A) in response to received a start enable indication during processing of a first of said processing modules, enable said computer to pause processing in connection with said first of said processing modules; and (B) after receiving start enable indications from others of said processing modules, enable the computer to resume processing in connection with said first of said processing modules and provide a start indication to said shared processing resource. 21. A method as defined in claim 20 in which each processing module is further configured to, after enabling said computer to generate respective start enable indications in connection therewith, enable the computer to generate a wait indication and pauses execution, the synchronization control module being configured to enable the computer to, in turn, resume processing in connection with all of the processing modules after respective wait indications have been generated in connection therewith. tion of the frequency bins; shifting the signal characteristic associated with the first region in the frequency domain representation to a second region in the frequency domain representation, wherein the second region comprises at least a second portion of the frequency bins, and therein forming an adjusted frequency domain representation; and transforming the adjusted frequency domain representation to a time domain signal. 2. The method of claim 1 wherein the signal characteristic is an amplitude characteristic and the step of identifying comprises a step of identifying the at least one frequency bin wherein the amplitude characteristic associated with the at least one frequency bin has a value greater than the amplitude characteristic associated with any of two adjacent lower frequency bins or two adjacent higher frequency bins. 3. The method of claim 2 wherein the step of defining comprises a step of defining the first region associated with the at least one frequency bin, wherein the first region is defined by a portion of the total frequency bins between the at least one frequency bin and at least a second frequency bin. 4. The method of claim 3 wherein the step of defining comprises a step of defining the first region associated with the at least one frequency bin, wherein the first region is defined by a portion of the total frequency bins between the at least one frequency bin and the at least a second frequency bin, wherein the amplitude characteristic associated with the at least a second frequency bin has a value greater than the amplitude characteristic associated with any of two adjacent lower frequency bins or two adjacent higher frequency bins. 5. The method of claim 4 wherein the step of defining comprises a step of defining the first region associated with the at least one frequency bin, wherein the first region is defined by one half of the total frequency bins between the at least one frequency bin and the at least a second frequency bin. 6. The method of claim 4 wherein the step of defining comprises a step of defining the first region associated with the at least one frequency bin, wherein the first region is defined by at least a third frequency bin having an amplitude characteristic with a minimum value as compared to other frequency bins between the at least one frequency bin and the at least a second frequency bin. 7. The method of claim 2 wherein the step of shifting comprises a step of shifting the amplitude characteristic associated with the first region in the frequency domain representation an integer number of frequency bins to the second region in the frequency domain representation, wherein the second region comprises at least a second portion of the frequency bins, and therein forming the adjusted frequency domain representation. 8. The method of claim 7 wherein the step of shifting further comprises a step of adjusting a phase characteristic associated with each bin in the first region by a multiple of π. 9. The method of claim 2 wherein the step of shifting comprises a step of shifting the amplitude characteristic associated with the first region in the frequency domain representation a non-integer number of frequency bins to the second region in the frequency domain representation, wherein the second region comprises at least a second portion of the frequency bins, and therein forming the adjusted frequency domain representation. 10. The method of claim 9 wherein the step of shifting comprises a step of shifting the amplitude characteristic associated with the first region in the frequency domain representation a non-integer number of frequency bins to the second region in the frequency domain representation using a linear interpolation algorithm, wherein the second region comprises at least a second portion of the frequency bins, and therein forming the adjusted frequency domain representation. 11. The method of claim 2 wherein the step of shifting comprises a step of copying the a mplitude characteristic associated with the first region in the frequency domain representation to the second region in the frequency domain representation, wherein the second region comprises at least a second portion of the frequency bins, and therein forming the adjusted frequency domain representation. 12. Apparatus for pitch-shifting an audio signal comprising: a transform module having logic to receive the signal and to produce a frequency domain representation of the signal, wherein the frequency domain representation comprises at least one signal characteristic associated with a plurality of frequency bins; a detector coupled to the transform module having logic to receive the frequency domain representation of the signal and to detect at least one frequency bin from the plurality of frequency bins based on the signal characteristics of multiple frequency bins, the detector further comprising logic to identify a first region comprising at least a first portion of the frequency bins associated with the at least one frequency bin; a frequency processor coupled to the detector and having logic to receive the frequency domain representation and to shift the signal characteristic associated with the first region to a second region, wherein the second region comprises at least a second portion of the frequency bins and therein forming an adjusted frequency domain representation; and an inverse transform module coupled to the frequency processor and having logic to receive the adjusted frequency domain representation and to transform the adjusted frequency domain representation to a time domain signal. 13. The apparatus of claim 12 wherein the signal characteristic is an amplitude characteristic and the detector further comprises logic to detect the at least one frequency bin, wherein the amplitude characteristic associated with the at least one frequency bin has a value greater than the amplitude characteristic associated with any of two adjacent lower frequency bins or two adjacent higher frequency bins, respectively. 14. The apparatus of claim 13 wherein the detector further comprises logic to detect at least a second frequency bin, wherein the amplitude characteristic associated with the at least a second frequency bin has a value greater than the amplitude characteristic associated with any of two adjacent lower frequency bins or two adjacent higher frequency bins, respectively. 15. The apparatus of claim 14 wherein the detector further comprises logic to identify the first region, wherein a boundary of the first region is defined by one half of the total frequency bins between the at least one frequency bin and the at least a second frequency bin. 16. The apparatus of claim 14 wherein the detector further comprises logic to identify the first region, wherein a boundary of the first region is defined by at least a third frequency bin, wherein the at least a third frequency bin has an amplitude characteristic with a minimum value relative to other frequency bins between the at least one frequency bin and the second frequency bin. 17. The apparatus of claim 13 wherein the frequency processor includes logic to shift the amplitude characteristic associated with the first region by an integer number of frequency bins to the second region, wherein the second region comprises at least a second portion of the frequency bins, and therein forming the adjusted frequency domain representation. 18. The apparatus of claim 17 wherein the frequency processor includes logic to adjust a phase characteristic associated with each bin in the first region by a multiple of π. 19. The apparatus of claim 13 wherein the frequency processor includes logic to shift the amplitude characteristic associated with the first region by a non-integer number of frequency bins to the second region, wherein the second region comprises at least a second portion of the frequency bins and therein forming an adjusted frequency domain representation. 20. T he apparatus of claim 19 wherein the frequency processor includes logic to shift the amplitude characteristic associated with the first region by a non-integer number of frequency bins to the second region by using an interpolation algorithm, and therein forming the adjusted frequency domain representation. 21. The apparatus of claim 13 wherein the frequency processor comprises logic to copy the amplitude characteristic associated with the first region to the second region, wherein the second region comprises at least a second portion of the frequency bins, and therein forming the adjusted frequency domain representation. 22. A method for pitch-shifting an audio signal comprising: converting the audio signal to a frequency domain representation, wherein the frequency domain representation comprises amplitude and phase values associated with a plurality of frequency bins; identifying at least one peak in the frequency domain representation based on the amplitude values of multiple frequency bins; defining a region of frequency bins associated with the at least one peak; shifting the region to a new region in the frequency domain representation, therein forming an adjusted frequency domain representation; and transforming the adjusted frequency domain representation to a time domain signal. 23. The method of claim 22 wherein the step of identifying comprises a step of identifying the at least one peak in the frequency domain representation, wherein the at least one peak has an amplitude value greater than the amplitude value of any of two adjacent lower frequency bins or two adjacent higher frequency bins. 24. The method of claim 22 wherein the step of defining comprises a step of defining the region of frequency bins for the at least one peak, wherein the region is defined by one half the number of frequency bins between the at least one peak and at least a second peak. 25. The method of claim 22 wherein the step of defining comprises a step of defining the region of frequency bins for the at least one peak, wherein the region is defined by the frequency bin located between the at least one peak and at least a second peak and having a minimum amplitude value. 26. The method of claim 22 wherein the step of shifting comprises a step of shifting the region an integer number of frequency bins to the new region in the frequency domain representation, therein forming the adjusted frequency domain representation. 27. The method of claim 26 wherein the step of shifting further comprises a step of adjusting a phase characteristic associated with each bin in the region by a multiple of π. 28. The method of claim 22 wherein the step of shifting comprises a step of shifting the region a non-integer number of frequency bins to the new region in the frequency domain representation, therein forming the adjusted frequency domain representation. 29. The method of claim 28 wherein the step of shifting comprises a step of shifting the region a non-integer number of frequency bins to the new region in the frequency domain using an interpolation algorithm, and therein forming the adjusted frequency domain representation. 30. The method of claim 22 wherein the region is a first region and the step of shifting comprises steps of: identifying at least a second peak in the frequency domain representation; defining a second region of frequency bins associated with the at least a second peak; and shifting the first region and the second region a different number of frequency bins to form the adjusted frequency domain representation. 31. The method of claim 22 wherein the step of shifting comprises a step of copying the region to the new region in the frequency domain, and therein forming the adjusted frequency domain representation. displaying a plurality of display screens to a user of said data device, input included on said housing for inputting at least one of user response data and user commands to said data device, a processor contained within said housing which is adapted to control the operation of said data device, memory means coupled to said processor which is adapted to store operating software for operating said data device and an application-specific input text file to be interpreted by said operating software, said input program by itself defining said display screens for said data device, whereby said data device can be programmed to be used for the plurality of different applications solely by modifying the input text file, and data device communications means included on said housing for a communications between said data device and computer; creating said input text file via said computer; connecting said device to said computer via said data device communications means and said computer communications means; transferring said input text file from said computer to said memory means of said data device; creating an output table within said computer directly from said input text file without the need for additional programming; transferring said user response data inputted to said data device to said output table without said computer; and analyzing said user response data stored in said output table via data analysis means stored within said computer. 2. A data device, comprising: a housing; display mean s included on said housing for displaying a plurality of display screens to a user of said data device; input means included on said housing for inputting at least one of user response data and user commands to said data device; a processor contained within said housing which is adapted to control the operation of said data device; and memory means coupled to said processor for storing operating software for operating said data device and for storing an application-specific input text file to be interpreted by said operating software which by itself defines said display screens for said data device, whereby said data device can be programmed and reprogrammed to be used for a plurality of different applications solely by modifying the input text file, wherein the input text file comprises a plurality of screen fields into which a plurality of screen definitions are stored, and at least one link field into which a link event is stored, the occurrence of which causes the display screen displayed by the data device to change. 3. The data device of claim 2, wherein the plurality of screen fields comprises a screen identification field for storing a unique number assigned to each display screen of the data device, a screen style field for storing a plurality of different screen styles, and a screen change field for storing a screen change event, the occurrence of which causes the screen displays to change in a predetermined period of time. 4. The data device of claim 2, further comprising communications means included on said housing for allowing communication between said data device and a remote computer, such that said input text file may be transferred from said computer to said data device. 5. An interactive computer system, comprising: a data device, said data device comprising: a housing; display means included on said housing for displaying a plurality of display screens to a user of said data device; input means included on said housing for inputting at least one of user response data and user commands to said data device; a processor contained within said housing which is adapted to control the operation of said data device; memory means coupled to said processor for storing operating software for operating said data device and for storing an application specific input text file to be interpreted by said operating software which by itself defines said display screens for said data device; and data device com
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