IPC분류정보
국가/구분 |
United States(US) Patent
등록
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국제특허분류(IPC7판) |
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출원번호 |
US-0698830
(2000-10-27)
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발명자
/ 주소 |
- Gates, George C.
- Gates, Rod S.
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출원인 / 주소 |
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대리인 / 주소 |
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인용정보 |
피인용 횟수 :
13 인용 특허 :
102 |
초록
▼
A bag filling and sealing machine includes a bag holder, a bag opening and filling station, and a sealing station. The bag holder holds wicketed bags in a manner that allows the bags to be easily torn from the holder. A funnel assembly successively opens each bag, tears the bag from the bag holder,
A bag filling and sealing machine includes a bag holder, a bag opening and filling station, and a sealing station. The bag holder holds wicketed bags in a manner that allows the bags to be easily torn from the holder. A funnel assembly successively opens each bag, tears the bag from the bag holder, fills the bag with material, and releases the bag to a grabber assembly. The grabber assembly engages the sides of the bag while the bag is attached to a funnel assembly and later pulls the sides of the bag away from each other so that the top of the bag is closed and ready to seal when the bag is delivered to a sealing apparatus. The grabber assembly moves in a manner so as to minimize the lost height when moving from the filling station to the sealing station.
대표청구항
▼
A bag filling and sealing machine includes a bag holder, a bag opening and filling station, and a sealing station. The bag holder holds wicketed bags in a manner that allows the bags to be easily torn from the holder. A funnel assembly successively opens each bag, tears the bag from the bag holder,
A bag filling and sealing machine includes a bag holder, a bag opening and filling station, and a sealing station. The bag holder holds wicketed bags in a manner that allows the bags to be easily torn from the holder. A funnel assembly successively opens each bag, tears the bag from the bag holder, fills the bag with material, and releases the bag to a grabber assembly. The grabber assembly engages the sides of the bag while the bag is attached to a funnel assembly and later pulls the sides of the bag away from each other so that the top of the bag is closed and ready to seal when the bag is delivered to a sealing apparatus. The grabber assembly moves in a manner so as to minimize the lost height when moving from the filling station to the sealing station. being processed with an operation designated by the input command. 5. A semiconductor memory device according to claim 1, comprising a control section for, after the command is input, controlling the state information, stored in the plurality of status registers, to be externally output in accordance with a read control signal which is input to an external control terminal. 6. A semiconductor memory device according to claim 1, wherein the first data bus has a width which is equal to or less than a width of the second data bus. 7. A semiconductor memory device including a plurality of memory arrays which are independently operable and having a function of transferring data between the plurality of memory arrays, the semiconductor memory device comprising: a plurality of status registers for storing state information of the plurality of memory arrays; a first switching circuit for receiving data from the plurality of status registers, and selectively outputting the data from at least one of the plurality of status registers to a first data bus; and a second switching circuit for receiving the data on the first data bus and data from a sense amplifier, and selectively outputting either one of the data to a second data bus. 8. An information device for performing at least one of a data transfer operation and a memory operation using a semiconductor memory device according to claim 1. 9. A semiconductor memory device according to claim 7, wherein an input command controls an operation, the semiconductor memory device further comprising a command state machine for decoding the input command and outputting the decoding result, wherein the first switching circuit and the second switching circuits are controlled by the decoding result output by the command state machine. 10. A semiconductor memory device according to claim 9, wherein the plurality of status registers include a first status register group including at least one status register for storing state information regarding an operation common to the semiconductor memory device, and a second status register group including at least one status register for storing state information regarding a data transfer operation between the plurality of memory arrays. 11. A semiconductor memory device according to claim 7, wherein the plurality of status registers include a first status register group including at least one status register for storing state information regarding an operation common to the semiconductor memory device, and a second status register group including at least one status register for storing state information regarding a data transfer operation between the plurality of memory arrays. 12. A semiconductor memory device according to claim 11, wherein the first and second status register groups each include information which identifies whether the status register belongs to the first status register group or the second status register group. 13. A semiconductor memory device according to claim 12, wherein the first and second status register groups each include information which exclusively identifies the respective status register. 14. A semiconductor memory device according to claim 11, wherein the first and second status register groups each include information which exclusively identifies the respective status register. 15. A semiconductor memory device according to claim 11, wherein the second status register group includes information on an address which is currently being processed with an operation designated by the command. 16. A semiconductor memory device according to claim 11, comprising a control section for, after the command is input, controlling the state information, stored in the first and second status register groups, to be externally output in accordance with a read control signal which is input to an external control terminal. 17. A semiconductor memory device according to claim 11, further comprising a write state machine for receiving t
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