초록 ▼

Bonding pads for integrated circuits include first and second spaced apart conductive layers, a third continuous conductive layer between the first and second spaced apart and an array of unaligned spaced apart insulating islands in the third continuous conductive layer and extending therethrough su

Bonding pads for integrated circuits include first and second spaced apart conductive layers, a third continuous conductive layer between the first and second spaced apart and an array of unaligned spaced apart insulating islands in the third continuous conductive layer and extending therethrough such that sidewalls of the array of insulating islands are surrounded by the third continuous conductive layer, rows of unaligned spaced apart insulating islands. The array can include rows of unaligned spaced apart insulating islands and columns of unaligned spaced apart insulating islands. The array of unaligned spaced apart insulating islands can also include a first insulating island having a first edge in a first direction and a second insulating island, adjacent to the first insulating island in the first direction having a second edge in the first direction that is unaligned with first edge.

대표청구항 ▼

Bonding pads for integrated circuits include first and second spaced apart conductive layers, a third continuous conductive layer between the first and second spaced apart and an array of unaligned spaced apart insulating islands in the third continuous conductive layer and extending therethrough su

Bonding pads for integrated circuits include first and second spaced apart conductive layers, a third continuous conductive layer between the first and second spaced apart and an array of unaligned spaced apart insulating islands in the third continuous conductive layer and extending therethrough such that sidewalls of the array of insulating islands are surrounded by the third continuous conductive layer, rows of unaligned spaced apart insulating islands. The array can include rows of unaligned spaced apart insulating islands and columns of unaligned spaced apart insulating islands. The array of unaligned spaced apart insulating islands can also include a first insulating island having a first edge in a first direction and a second insulating island, adjacent to the first insulating island in the first direction having a second edge in the first direction that is unaligned with first edge. witching elements and second ends connected to said second wiring pattern; an external terminal connected to said second wiring pattern for electrically connecting said second main electrodes of said plurality of switching elements with the exterior through said second wiring pattern; and a conductor electrically connecting said second main electrodes of said plurality of switching elements with each other without through said second wiring pattern. 2. The semiconductor device according to claim 1, wherein said conductor includes: a third wiring pattern arranged on said main surface isolatedly from said second wiring pattern, and a plurality of second conductor wires having first ends connected to said second main electrodes of said plurality of switching elements and second ends connected to said third wiring pattern. 3. The semiconductor device according to claim 2, wherein said second wiring pattern extends along the direction of arrangement of said plurality of switching elements, and said third wiring pattern extends along the direction of arrangement of said plurality of switching elements on the side opposite to said second wiring pattern through said plurality of switching elements. 4. The semiconductor device according to claim 3, wherein said third wiring pattern is adjacent to said plurality of switching elements without the remaining wiring patterns interposed therebetween. 5. The semiconductor device according to claim 2, wherein said third wiring pattern has a repetitive bent portion. 6. The semiconductor device according to claim 1, wherein said conductor includes: a third conductor wire directly connecting said second main electrodes of said plurality of switching elements with each other. 7. The semiconductor device according to claim 6, wherein said second wiring pattern extends along the direction of arrangement of said plurality of switching elements, said plurality of first conductor wires are arranged in a direction substantially perpendicular to said direction of arrangement, and said third conductor wire is arranged along said direction of arrangement. 8. The semiconductor device according to claim 7, wherein said third conductor wire is connected with said second main electrodes of said plurality of switching elements on portions farther from said second wiring pattern than said first ends of said plurality of first conductor wires. 9. The semiconductor device according to claim 2, further comprising: a fourth wiring pattern arranged on said main surface, a plurality of fourth conductor wires having first ends connected to control electrodes of said plurality of switching elements and second ends connected to said fourth wiring pattern, and a voltage clamping element having a first end connected to said third wiring pattern and a second end connected to said fourth wiring pattern. 10. A semiconductor device comprising: a substrate having a main surface; a first wiring pattern arranged on said main surface; a plurality of switching elements arranged on said first wiring pattern so that first main electrodes thereof are electrically connected with each other; a second wiring pattern arranged on said main surface; a plurality of first conductor wires having first ends connected to second main electrodes of said plurality of switching elements and second ends connected to said second wiring pattern; an external terminal connected to said second wiring pattern for electrically connecting said second main electrodes of said plurality of switching elements with the exterior through said second wiring pattern; and a voltage clamping element electrically connected between control electrodes and said second main electrodes of said plurality of switching elements. 11. A semiconductor device comprising: a substrate having a main surface; a first wiring pattern arranged on said main surface; a plurality of switching elements arranged on said fi rst wiring pattern so that first main electrodes are electrically connected with each other; a second wiring pattern arranged on said main surface to extend along the direction of arrangement of said plurality of switching elements; a plurality of first conductor wires having first ends connected to second main electrodes thereof of said plurality of switching elements and second ends connected to said second wiring pattern; an external terminal connected to said second wiring pattern for electrically connecting said second main electrodes of said plurality of switching elements with the exterior through said second wiring pattern; a plurality of diodes, provided in the same number as said plurality of switching elements, arranged on said first wiring pattern so that first electrodes thereof are electrically connected with each other and arranged between said plurality of switching elements and said second wiring pattern to be adjacent to said plurality of switching elements in one-to-one correspondence; a plurality of second conductor wires having first ends connected to second electrodes of said plurality of diodes and second ends connected to said second wiring pattern; and a plurality of third conductor wires having first ends connected to said second main electrodes of said plurality of switching elements, intermediate potions connected to said second electrodes of at least part of said plurality of diodes and second ends connected to said second wiring pattern thereby electrically connecting all said second main electrodes of said plurality of switching elements with each other without through said second wiring pattern. 12. The semiconductor device according to claim 1, wherein said second wiring pattern extends along the direction of arrangement of said plurality of switching elements, said second wiring pattern is formed with a slit extending along said direction of arrangement so as to leave a coupling portion on the side of a first end of said direction of arrangement while as to leave no coupling portion on the side of a second end, said second ends of said plurality of first conductor wires are connected to said second wiring pattern on a first portion closer to said plurality of switching elements than said slit, and said external terminal is connected to said second wiring pattern on said coupling portion on the side of said first end, said semiconductor device further comprising: another external terminal connected to said second wiring pattern on the side of said second end in a second portion farther from said plurality of switching elements than said slit for electrically connecting said second main electrodes of said plurality of switching elements with the exterior through said second wiring pattern. 13. The semiconductor device according to claim 10, wherein said second wiring pattern extends along the direction of arrangement of said plurality of switching elements, said second wiring pattern is formed with a slit extending along said direction of arrangement so as to leave a coupling portion on the side of a first end of said direction of arrangement while as to leave no coupling portion on the side of a second end, said second ends of said plurality of first conductor wires are connected to said second wiring pattern on a first portion closer to said plurality of switching elements than said slit, and said external terminal is connected to said second wiring pattern on said coupling portion on the side of said first end, said semiconductor device further comprising: another external terminal connected to said second wiring pattern on the side of said second end in a second portion farther from said plurality of switching elements than said slit for electrically connecting said second main electrodes of said plurality of switching elements with the exterior through said second wiring pattern. 14. The semiconductor device according to claim 11, wherein said second wirin