IPC분류정보
국가/구분 |
United States(US) Patent
등록
|
국제특허분류(IPC7판) |
|
출원번호 |
US-0587720
(2000-06-05)
|
발명자
/ 주소 |
|
출원인 / 주소 |
- Agilent Technologies, Inc.
|
인용정보 |
피인용 횟수 :
6 인용 특허 :
9 |
초록
▼
A method of fabricating a diode device, such as a PIN diode, includes forming top and bottom regions of opposite conductivity types and includes anisotropically etching into the top surface to form a pit having side walls that converge with approach to the bottom surface. However, the pit does not e
A method of fabricating a diode device, such as a PIN diode, includes forming top and bottom regions of opposite conductivity types and includes anisotropically etching into the top surface to form a pit having side walls that converge with approach to the bottom surface. However, the pit does not extend to the bottom surface. In the PIN diode embodiment, the pit terminates within an intrinsic region that separates a bottom surface diffusion region from a diffusion region along the walls of the anisotropically etched pit. The anisotropic etching approach provides a degree of self regulation with regard to the geometries of the pit. A process flow of steps is described, which allows thicker and larger diameter wafers to be used in the formation of an array of such diode device.
대표청구항
▼
A method of fabricating a diode device, such as a PIN diode, includes forming top and bottom regions of opposite conductivity types and includes anisotropically etching into the top surface to form a pit having side walls that converge with approach to the bottom surface. However, the pit does not e
A method of fabricating a diode device, such as a PIN diode, includes forming top and bottom regions of opposite conductivity types and includes anisotropically etching into the top surface to form a pit having side walls that converge with approach to the bottom surface. However, the pit does not extend to the bottom surface. In the PIN diode embodiment, the pit terminates within an intrinsic region that separates a bottom surface diffusion region from a diffusion region along the walls of the anisotropically etched pit. The anisotropic etching approach provides a degree of self regulation with regard to the geometries of the pit. A process flow of steps is described, which allows thicker and larger diameter wafers to be used in the formation of an array of such diode device. t al., 428/068; US-4395459, 19830700, Herschdorfer et al., 428/391; US-4409280, 19831000, Wiley et al.; US-4411931, 19831000, Duong, 427/054.1; US-4417008, 19831100, Salensky et al., 523/442; US-4418109, 19831100, Miller, Jr. et al., 428/142; US-4443577, 19840400, Higgins et al., 524/590; US-4450194, 19840500, Kauffman et al., 428/172; US-4451605, 19840500, Theodore, 524/423; US-4456643, 19840600, Colyer, 428/156; US-4464423, 19840800, LaBinaca et al., 427/244; US-4491616, 19850100, Schmidle et al., 428/158; US-4501790, 19850200, Aizawa et al., 428/283; US-4520062, 19850500, Ungar et al., 428/148; US-4526823, 19850700, Farrell et al., 428/035; US-4528231, 19850700, Lund, 428/148; US-4529650, 19850700, Martinez, 428/336; US-4530856, 19850700, Kauffman et al., 427/197; US-4547245, 19851000, Colyer, 156/220; US-RE32152, 19860500, Scher et al., 428/148; US-4588545, 19860500, Kauffman et al., 264/046.4; US-4595621, 19860600, Valenti et al., 428/159; US-4647647, 19870300, Haubennestel et al., 528/083; US-4650819, 19870300, Nakamoto et al., 523/223; US-4689102, 19870800, Prawdzik et al., 156/235; US-4698258, 19871000, Harkins, Jr., 428/285; US-4747901, 19880500, Becker et al., 156/220; US-4756951, 19880700, Wang et al., 428/204; US-4762752, 19880800, Haubennestel et al., 428/407; US-4795796, 19890100, Haubennestel et al., 528/028; US-4816314, 19890300, Prawdzik et al., 156/235; US-4857111, 19890800, Haubennestel et al., 106/504; US-4863782, 19890900, Wang
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