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A method is provided for making ultra-shallow diffused junctions using an elemental dopant. A semiconductor wafer is cleaned for providing a clean reaction surface. The cleaned wafer in loaded onto a stage located in a doping system. A quantity of elemental dopant atoms are placed in a partially enc

A method is provided for making ultra-shallow diffused junctions using an elemental dopant. A semiconductor wafer is cleaned for providing a clean reaction surface. The cleaned wafer in loaded onto a stage located in a doping system. A quantity of elemental dopant atoms are placed in a partially enclosed elemental dopant source which is within a secondary vacuum enclosure. A quantity of the elemental dopant atoms having thermal velocities are deposited onto a surface of the wafer, and the wafer is heated for diffusing the elemental dopant into the wafer. In one embodiment, the heating is conducted by heating the wafer in ultra-high vacuum for diffusing the portion of the doping atoms into the wafer, and the deposition and heating occur simultaneously. In another embodiment, the surface of the wafer is hydrogen terminated, the wafer is removed from the UHV system, and the heating of the wafer is conducted outside of the UHV system by heating the wafer in a furnace. Preferably, a cap layer is added to protect the wafer. The method results in ultra-shallow diffused junctions having a depth of as shallow as about 10 nm.

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A method is provided for making ultra-shallow diffused junctions using an elemental dopant. A semiconductor wafer is cleaned for providing a clean reaction surface. The cleaned wafer in loaded onto a stage located in a doping system. A quantity of elemental dopant atoms are placed in a partially enc

A method is provided for making ultra-shallow diffused junctions using an elemental dopant. A semiconductor wafer is cleaned for providing a clean reaction surface. The cleaned wafer in loaded onto a stage located in a doping system. A quantity of elemental dopant atoms are placed in a partially enclosed elemental dopant source which is within a secondary vacuum enclosure. A quantity of the elemental dopant atoms having thermal velocities are deposited onto a surface of the wafer, and the wafer is heated for diffusing the elemental dopant into the wafer. In one embodiment, the heating is conducted by heating the wafer in ultra-high vacuum for diffusing the portion of the doping atoms into the wafer, and the deposition and heating occur simultaneously. In another embodiment, the surface of the wafer is hydrogen terminated, the wafer is removed from the UHV system, and the heating of the wafer is conducted outside of the UHV system by heating the wafer in a furnace. Preferably, a cap layer is added to protect the wafer. The method results in ultra-shallow diffused junctions having a depth of as shallow as about 10 nm. same stacked-gate structure as the memory cells. 13. The non-volatile semiconductor memory device according to claim 12, further comprising transistors each having a first gate electrode formed on the semiconductor substrate via a third insulating film and a second gate electrode formed as touching the first gate electrode. 14. The non-volatile semiconductor memory device according to claim 13, wherein the third gate insulating film of each transistor includes at least two types of films of different thickness, the third gate insulating film for a transistor of the transistors, for high-withstand voltage application, being thicker than the first insulating film, and the third gate insulating film for another transistor of the transistors, for low-voltage application, having the same thickness or being thinner than the first insulating film. 15. The non-volatile semiconductor memory device according to claim 13, wherein the first gate electrode is formed of two or more conductive layers electrically connected to each other like the charge-storage layer, a side end portion of the lowest conductive layer of the first gate electrode, that touches the isolation region, meeting a side wall of each trench. 16. The non-volatile semiconductor memory device according to claim 13, wherein a plurality of conductive layers that constitute the first gate electrode are made of the same material as the plurality of conductive layers that co