$\require{mediawiki-texvc}$

연합인증

연합인증 가입 기관의 연구자들은 소속기관의 인증정보(ID와 암호)를 이용해 다른 대학, 연구기관, 서비스 공급자의 다양한 온라인 자원과 연구 데이터를 이용할 수 있습니다.

이는 여행자가 자국에서 발행 받은 여권으로 세계 각국을 자유롭게 여행할 수 있는 것과 같습니다.

연합인증으로 이용이 가능한 서비스는 NTIS, DataON, Edison, Kafe, Webinar 등이 있습니다.

한번의 인증절차만으로 연합인증 가입 서비스에 추가 로그인 없이 이용이 가능합니다.

다만, 연합인증을 위해서는 최초 1회만 인증 절차가 필요합니다. (회원이 아닐 경우 회원 가입이 필요합니다.)

연합인증 절차는 다음과 같습니다.

최초이용시에는
ScienceON에 로그인 → 연합인증 서비스 접속 → 로그인 (본인 확인 또는 회원가입) → 서비스 이용

그 이후에는
ScienceON 로그인 → 연합인증 서비스 접속 → 서비스 이용

연합인증을 활용하시면 KISTI가 제공하는 다양한 서비스를 편리하게 이용하실 수 있습니다.

Methods for mask repattern process 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/44
출원번호 US-0017419 (2001-12-12)
발명자 / 주소
  • Farnworth, Warren M.
출원인 / 주소
  • Micron Technology, Inc.
대리인 / 주소
    TraskBritt
인용정보 피인용 횟수 : 7  인용 특허 : 33

초록

The present invention relates to an improved method for forming a UBM pad and solder bump connection for a flip-chip which eliminates at least two mask steps required in standard UBM pad forming processes when repatterning the bond pad locations.

대표청구항

The present invention relates to an improved method for forming a UBM pad and solder bump connection for a flip-chip which eliminates at least two mask steps required in standard UBM pad forming processes when repatterning the bond pad locations. g a first absorption coefficient relative to the wave

이 특허에 인용된 특허 (33)

  1. Ichikawa Matsuo,JPX, Bonding pad structures for semiconductor integrated circuits.
  2. Akagawa Masatoshi (Nagano JPX), Chip sized semiconductor device.
  3. Honn ; James J. ; Stuby ; Kenneth P., Electrical package for LSI devices and assembly process therefor.
  4. Dux John B. (Millbrook NY) Poetzinger Janet L. (Pleasant Valley NY) Prestipino Roseanne M. (Beacon NY) Siefering Kevin L. (Cary NC), Fabrication of discrete thin film wiring structures.
  5. Pasch Nicholas F. (Pacifica CA), Fabrication of substrates for multi-chip modules.
  6. Volfson David (Worcester MA) Senturia Stephen D. (Boston MA), High-density, multi-level interconnects, flex circuits, and tape for tab.
  7. Tai King L. (Berkeley Heights NJ), Integrated circuit chip-and-substrate assembly.
  8. Wilson Arthur M. (Richardson TX), Integrated circuit product having a polyimide film interconnection structure.
  9. Moresco Larry L. (San Carlos CA) Love David G. (Pleasanton CA) Wang Wen-Chou V. (Cupertino CA), Interconnect capacitors.
  10. Corisis David ; Moden Walter, Interconnect for packaging semiconductor dice and fabricating BGA packages.
  11. Rinne Glenn A. ; Mis Joseph Daniel, Key-shaped solder bumps and under bump metallurgy.
  12. Farnworth Warren M., Mask repattern process.
  13. Farnworth Warren M., Mask repattern process.
  14. Farnworth Warren M., Mask repattern process.
  15. Farnworth Warren M., Mask repattern process.
  16. Farnworth Warren M., Mask repattern process.
  17. Warren M. Farnworth, Mask repattern process.
  18. Reele Samuel (Rochester NY) Pian Thomas R. (Rochester NY), Method for creating substrate electrodes for flip chip and other applications.
  19. Elenius Peter ; Hollack Harry, Method for forming chip scale package.
  20. Kondo Kenji (Hoi JPX) Kunda Hachiro (Chiryu JPX) Sonobe Toshio (Okazaki JPX), Method for making a semiconductor device.
  21. Nishi Toshio (Fukuoka JPX) Wada Yoshiyuki (Onojo JPX) Kadokami Eigo (Kasuga JPX) Yoshinaga Seiichi (Kasuga JPX), Method for mounting electronic devices.
  22. Wilson Arthur M. (Richardson TX), Method for producing an integrated circuit product having a polyimide film interconnection structure.
  23. Akram Salman, Method of forming conductive bumps on die for flip chip applications.
  24. Lochon Henri (Saintry-sur-Seine FRX) Robert Georges (La Ferte-Alais FRX), Method of forming metal contact pads and terminals on semiconductor chips.
  25. Lin Paul T. (Austin TX), Method of transferring solder balls onto a semiconductor device.
  26. Wong Wah-Sang (Montebello CA) Gray William D. (Redondo Beach CA), Polyimide passivation of GaAs microwave monolithic integrated circuit flip-chip.
  27. Yerman Alexander J. (Scotia NY), Screenable power chip mosaics, a method for fabricating large power semiconductor chips.
  28. Nozawa Kazuhiko,JPX, Semiconductor device and method of manufacturing the same, circuit board and electronic instrument.
  29. Nobuaki Hashimoto JP, Semiconductor device and method of manufacturing the same, circuit board, and electronic instrument.
  30. Kobayashi Syoichi,JPX ; Koizumi Naoyuki,JPX ; Uehara Osamu,JPX ; Iizuka Hajime,JPX, Semiconductor device and process for producing same.
  31. Mori Katsunobu (Nara JPX), Semiconductor device having external electrodes formed in concave portions of an anisotropic conductive film.
  32. Sudo Toshio (Kawasaki JPX), Semiconductor integrated circuit device with optical transmit-receive means.
  33. Moore Kevin D. (Schaumburg IL) Missele Carl (Elgin IL), Solder bumping of integrated circuit die.

이 특허를 인용한 특허 (7)

  1. Lin, Mou-Shiung; Lin, I, Shih-Hsiung, Chip package having a chip combined with a substrate via a copper pillar.
  2. Lin,Shih Hsiung; Lin,Mou Shiung, Chip package with multiple chips connected by bumps.
  3. Kuo, Nick; Chou, Chiu-Ming; Chou, Chien-Kang; Lin, Chu-Fu, Chip structure with bumps and testing pads.
  4. Martinez, Liane; Topacio, Roden R.; Low, Yip Seng, Face-to-face (F2F) hybrid structure for an integrated circuit.
  5. Farnworth, Warren M., Mask repattern process.
  6. Chen, Yen-Ming; Lin, Chia-Fu; Fan, Yang-Tung; Huang, Hong-Wen; Chu, Cheng-Yu, Microelectronic fabrication with corrosion inhibited bond pad.
  7. Hara,Kazumi, Semiconductor chip, semiconductor device and electronic equipment including warpage control film, and manufacturing method of same.
섹션별 컨텐츠 바로가기

AI-Helper ※ AI-Helper는 오픈소스 모델을 사용합니다.

AI-Helper 아이콘
AI-Helper
안녕하세요, AI-Helper입니다. 좌측 "선택된 텍스트"에서 텍스트를 선택하여 요약, 번역, 용어설명을 실행하세요.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.

선택된 텍스트

맨위로