IPC분류정보
국가/구분 |
United States(US) Patent
등록
|
국제특허분류(IPC7판) |
|
출원번호 |
US-0690934
(2000-10-17)
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발명자
/ 주소 |
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출원인 / 주소 |
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대리인 / 주소 |
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인용정보 |
피인용 횟수 :
7 인용 특허 :
7 |
초록
▼
A multi-port computer register file has shared word lines for read and write ports and storage elements that power down during write operations. Assume that a register file in accordance with the present invention has R read ports and W write ports, and R is greater than W. In such a register file,
A multi-port computer register file has shared word lines for read and write ports and storage elements that power down during write operations. Assume that a register file in accordance with the present invention has R read ports and W write ports, and R is greater than W. In such a register file, each register will be accessed by W combined read/write word lines, a single direction line, and R-W read-only word lines. The direction line is asserted during a write operation, and is not asserted during a read operation, and also allows the storage elements comprising each register of the register file to be powered down or enter a high-impedance state during a write operation. During a read operation, the direction line remains deasserted and the storage elements remain powered up and active. For read ports sharing combined read/write word lines with write ports, the direction line is used as a multiplexer signal to enable a read operation at the read port represented by the combined read/write word line. For read ports that are not shared, a read-only word line is used to enable the read operation. During a write operation, the direction line is asserted and the storage elements are powered down or enter a high-impedance state. The direction line is used as a multiplexer signal to enable a write operation at the write port represented by the combined read/write word line. When the write operation ends, the direction line is deasserted, and the storage elements are powered up or leave the high-impedance state, thereby retaining the value written to the storage elements. The present invention provides two important benefits over the prior art. First, by powering down storage elements or placing storage elements in a high-impedance state during write operations, smaller transistors can be used to write values into storage elements. By using smaller transistors, the size and power requirements of the register file are reduced. Second, by using a direction line and combined word lines for read and write ports, the number of horizontal lines running across the register file are reduced.
대표청구항
▼
A multi-port computer register file has shared word lines for read and write ports and storage elements that power down during write operations. Assume that a register file in accordance with the present invention has R read ports and W write ports, and R is greater than W. In such a register file,
A multi-port computer register file has shared word lines for read and write ports and storage elements that power down during write operations. Assume that a register file in accordance with the present invention has R read ports and W write ports, and R is greater than W. In such a register file, each register will be accessed by W combined read/write word lines, a single direction line, and R-W read-only word lines. The direction line is asserted during a write operation, and is not asserted during a read operation, and also allows the storage elements comprising each register of the register file to be powered down or enter a high-impedance state during a write operation. During a read operation, the direction line remains deasserted and the storage elements remain powered up and active. For read ports sharing combined read/write word lines with write ports, the direction line is used as a multiplexer signal to enable a read operation at the read port represented by the combined read/write word line. For read ports that are not shared, a read-only word line is used to enable the read operation. During a write operation, the direction line is asserted and the storage elements are powered down or enter a high-impedance state. The direction line is used as a multiplexer signal to enable a write operation at the write port represented by the combined read/write word line. When the write operation ends, the direction line is deasserted, and the storage elements are powered up or leave the high-impedance state, thereby retaining the value written to the storage elements. The present invention provides two important benefits over the prior art. First, by powering down storage elements or placing storage elements in a high-impedance state during write operations, smaller transistors can be used to write values into storage elements. By using smaller transistors, the size and power requirements of the register file are reduced. Second, by using a direction line and combined word lines for read and write ports, the number of horizontal lines running across the register file are reduced. shift registers, each having a control terminal coupled to receive the reference clock signal, a reset terminal coupled to receive the third flag signal, a data input terminal, and a data output terminal, the data input terminal of a first shift register in the plurality of shift registers having its data terminal coupled to receive a logic high signal, wherein the unlocked state of the third flag signal causes each of the plurality of shift registers to be reset. 15. In a delay locked loop circuit having a delay chain, a method of providing a delay adjustment signal for controlling a delay time, comprising: comparing a delayed clock signal generated by the delayed chain to a reference signal, thereby generating a first adjustment signal; applying a noise-compensating condition to the first adjustment signal, thereby generating a second adjustment signal; comparing the delayed clock signal and the reference signal, thereby generating a locking signal; when the locking signal is in a locked state, selecting the second adjustment signal as the delay adjustment signal; and when the locking signal is in an unlocked state selecting the first adjustment signal as the delay adjustment signal. 16. The method of claim 15, wherein applying a noise-compensating condition to the first adjustment signal comprises: counting a number of occurrences of the first adjustment signal; and generating the second adjustment signal when the number of occurrences exceeds a predetermined threshold. 17. The method of claim 15, wherein comparing the delayed clock signal and the reference signal comprises: delaying the reference signal by a predetermined time; comparing the delayed clock signal to the delayed reference signal; generating a first flag signal when the delayed clock signal arrives later than the reference clock signal; delaying the delayed clock signal by a predetermined time, thereby producing a second delayed clock signal; comparing the reference signal to the second delayed clock signal; generating a second flag signal when the reference signal arrives later than the delayed clock signal; and generating the locking signal based on the first and second flag signals. 18. The method of claim 15, further comprising: delaying for a predetermined time a transition of the locking signal to a locked state, while not delaying a transition of the locking signal to an unlocked state.
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