초록 ▼

A DMA transfer device has stream inputting means for receiving an encoded first stream; first stream storing means for storing the first stream; a main storage unit which stores the stream of said first stream storing means; first DMA transfer executing means,for executing a first DMA transfer

A DMA transfer device has stream inputting means for receiving an encoded first stream; first stream storing means for storing the first stream; a main storage unit which stores the stream of said first stream storing means; first DMA transfer executing means,for executing a first DMA transfer from said first stream storing means to said main storage unit; first DMA transfer controlling means for controlling said first DMA transfer executing means on the basis of an amount of data which are stored in said first stream storing means or a free capacity; a processing unit which produces a second stream from the first stream that is read out from said main storage unit, and which writes the second stream into said main storage unit; second stream storing means for storing the second stream of said main storage unit; second DMA transfer executing means for executing a second DMA transfer from said main storage unit to said second stream storing means; and second DMA transfer controlling means for controlling said second DMA transfer executing means on the basis of an amount of data which are stored in said second stream storing means or a free capacity.

대표청구항 ▼

A DMA transfer device has stream inputting means for receiving an encoded first stream; first stream storing means for storing the first stream; a main storage unit which stores the stream of said first stream storing means; first DMA transfer executing means,for executing a first DMA transfer

A DMA transfer device has stream inputting means for receiving an encoded first stream; first stream storing means for storing the first stream; a main storage unit which stores the stream of said first stream storing means; first DMA transfer executing means,for executing a first DMA transfer from said first stream storing means to said main storage unit; first DMA transfer controlling means for controlling said first DMA transfer executing means on the basis of an amount of data which are stored in said first stream storing means or a free capacity; a processing unit which produces a second stream from the first stream that is read out from said main storage unit, and which writes the second stream into said main storage unit; second stream storing means for storing the second stream of said main storage unit; second DMA transfer executing means for executing a second DMA transfer from said main storage unit to said second stream storing means; and second DMA transfer controlling means for controlling said second DMA transfer executing means on the basis of an amount of data which are stored in said second stream storing means or a free capacity. tion with respect to the first transaction according to a predetermined set of ordering rules. 5. The computer system as recited in claim 4, wherein the processing subsystem further comprises a memory coupled to a first of the plurality of processing nodes. 6. The computer system as recited in claim 6, wherein the first transaction is a posted write transaction for storing data within the memory. 7. The computer system as recited in claim 6, wherein the first processing node is configured to produce a first target done packet directed to the host bridge in response to the first transaction. 8. The computer system as recited in claim 7, wherein the first processing node is configured to produce the first target done packet after the first transaction has reached a point of coherency within the computer system. 9. The computer system as recited in claim 8, wherein the first transaction has reached the point of coherency within the computer system when the first transaction is: (i) ordered within the first processing node with respect to other transactions pending within the first processing node, and (ii) a coherency state with respect to the first transaction has been established in the other processing nodes. 10. The computer system as recited in claim 6, wherein the I/O node is part of an I/O subsystem comprising a plurality of I/O nodes serially interconnected via non-coherent communication links. 11. The computer system as recited in claim 10, wherein the second transaction is a flush command, and wherein the first and second transactions have a common source within the I/O subsystem, and wherein the flush command ensures posted write transactions issued prior to the flush command by the source have at least reached points of coherency within the computer system. 12. The computer system as recited in claim 11, wherein the second transaction is completed when the host bridge dispatches a second target done packet to the source of the flush command. 13. The computer system as recited in claim 12, wherein according to the predetermined set of ordering rules, the host bridge is configured to dispatch the second target done packet to the source of the flush command in response to receiving the first target done packet. 14. The computer system as recited in claim 4, wherein each of the processing nodes comprises a processor core configured to execute instructions of a predefined instruction set. 15. A method in a computer system comprising a processing subsystem and an input/output (I/O) subsystem, the method comprising: the I/O subsystem providing a first transaction and a second transaction to a host bridge of the processing subsystem; the host bridge dispatching the first transaction within the processing subsystem; and the host bridge dispatching the second transaction within the processing subsystem dependent upon progress of the first transaction within the processing subsystem and a predetermined set of ordering rules. 16. A method in a computer system comprising a processing subsystem and an input/output (I/O) subsystem, the method comprising: the I/O subsystem providing a first transaction and a second transaction to a host bridge of the processing subsystem; the host bridge dispatching the first transaction within the processing subsystem; and the host bridge delaying completion of the second transaction with respect to the first transaction according to a predetermined set of ordering rules. 17. A node comprising: a plurality of interface logic circuits, each of said plurality of interface logic circuits for coupling to a respective link, at least one of said respective links being a non-coherent link and remaining links being coherent links; and a host bridge coupled to receive a first transaction from the non-coherent link and a subsequent second transaction from the non-coherent link, wherein the host bridge is configured to generate a third transaction corresponding to the first transaction for