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Programmable ALU 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-009/00
출원번호 US-0280247 (1999-03-29)
발명자 / 주소
  • Callen, Greg S.
대리인 / 주소
    Rutan & Tucker, LLP
인용정보 피인용 횟수 : 72  인용 특허 : 16

초록

A programmable arithmetic and logic unit (ALU) comprising a plurality of data selectors, the data selectors having corresponding data input lines; a plurality of ALU function input lines wherein the number of ALU function input lines is equal to the number of data input lines on each of the data sel

대표청구항

A programmable arithmetic and logic unit (ALU) comprising a plurality of data selectors, the data selectors having corresponding data input lines; a plurality of ALU function input lines wherein the number of ALU function input lines is equal to the number of data input lines on each of the data sel

이 특허에 인용된 특허 (16)

  1. Jones ; Jr. Morris E. (Saratoga CA) Picard James A. (San Jose CA), Arithmetic logic unit for microprocessor with sign bit extend.
  2. Yokoyama Tatsuya (Machida JPX) Hirata Tetsuhiko (Machida JPX), Arithmetic-logic unit with modulo addition/substraction function and microprocessor using the same.
  3. Nakamura Norimitsu (Oume JPX), Central processing unit with improved ALU circuit control.
  4. Devine William T. (Ulster Park NY) Gianopulos William (West Hurley NY), Demand powered programmable logic array.
  5. DeHon Andre ; Knight ; Jr. Thomas F. ; Tau Edward ; Bolotski Michael ; Eslick Ian ; Chen Derrick ; Brown Jeremy, Dynamically programmable gate array with multiple contexts.
  6. McCollum John L. (Saratoga CA), Field programmable digital signal processing array integrated circuit.
  7. Wong Dale ; Phillips Christopher E. ; Cooke Laurence H., Integrated processor and programmable data path chip for reconfigurable computing.
  8. DeHon Andre ; Mirsky Ethan ; Knight ; Jr. Thomas F., Intermediate-grain reconfigurable processing device.
  9. Trimberger Stephen M., Method for compiling and executing programs for reprogrammable instruction set accelerator.
  10. Yamakawa Takeshi (Kikuchi JPX), Multivalued ALU.
  11. Miner Jay G. (Mtn. View CA) Dean Dave (Ukiah CA) Decuir Joseph C. (Albany CA) Nicholson Ronald H. (Sunnyvale CA) Tanaka Akio (Burlingame CA), Personal computer apparatus for block transfer of bit-mapped image data.
  12. Chan Andrew K. (Palo Alto CA) Birkner John M. (Portola Valley CA) Chua Hua-Thye (Los Altos Hills CA), Programmable application specific integrated circuit and logic cell therefor.
  13. Jennings ; III Earle W. (Richardson TX) Landers George H. (Mountain View CA), Programmable logic device.
  14. Purcell Stephen C. ; Thomson John Sheldon, Programmable logic unit for arithmetic, logic and equality functions.
  15. Alan David Marshall GB; Anthony Stansfield GB; Jean Vuillemin FR, Reconfigurable processor devices.
  16. Mahant-Shetti Shivaling S. (Richardson TX) Swamy Shobana (Los Angeles CA), Single integrated circuit having both a memory array and an arithmetic and logic unit (ALU).

이 특허를 인용한 특허 (72)

  1. Langhammer, Martin; Nguyen, Triet M.; Lin, Yi-Wen, Adder-rounder circuitry for specialized processing block in programmable logic device.
  2. Langhammer, Martin, Angular range reduction in an integrated circuit device.
  3. Langhammer, Martin, Calculation of trigonometric functions in an integrated circuit device.
  4. Langhammer, Martin, Calculation of trigonometric functions in an integrated circuit device.
  5. Langhammer, Martin, Calculation of trigonometric functions in an integrated circuit device.
  6. Langhammer, Martin, Calculation of trigonometric functions in an integrated circuit device.
  7. Langhammer, Martin, Combined adder and pre-adder for high-radix multiplier circuit.
  8. Langhammer, Martin, Combined floating point adder and subtractor.
  9. Mauer, Volker, Combined interpolation and decimation filter for programmable logic device.
  10. Langhammer, Martin, Computing floating-point polynomials in an integrated circuit device.
  11. Langhammer, Martin; Pasca, Bogdan, Computing floating-point polynomials in an integrated circuit device.
  12. Gonzalez, Ricardo E.; Rudell, Richard L.; Ghosh, Abhijit; Wang, Albert R., Configuring a multi-processor system.
  13. Langhammer, Martin, Configuring a programmable integrated circuit device to perform matrix multiplication.
  14. Langhammer, Martin, Configuring floating point operations in a programmable device.
  15. Langhammer, Martin, Configuring floating point operations in a programmable logic device.
  16. Leung, Wai-Bor; Lui, Henry Y., DSP block for implementing large multiplier on a programmable integrated circuit device.
  17. Williams,Kenneth M; Wang,Albert, Defining instruction extensions in a standard programming language.
  18. Demirsoy, Suleyman Sirri; Yi, Hyun, Digital signal processing circuit blocks with support for systolic finite-impulse-response digital filtering.
  19. Demirsoy, Suleyman Sirri; Yi, Hyun, Digital signal processing circuit blocks with support for systolic finite-impulse-response digital filtering.
  20. Demirsoy, Suleyman; Yi, Hyun, Digital signal processing circuit blocks with support for systolic finite-impulse-response digital filtering.
  21. Langhammer, Martin, Digital signal processing circuitry with redundancy and ability to support larger multipliers.
  22. Langhammer, Martin; Lin, Yi-Wen; Streicher, Keone, Digital signal processing circuitry with redundancy and bidirectional data paths.
  23. Langhammer, Martin, Discrete Fourier Transform in an integrated circuit device.
  24. Langhammer, Martin, Double-clocked specialized processing block in an integrated circuit device.
  25. Johnson, Scott D., Extension adapter.
  26. Chou, Shin-I, High-rate interpolation or decimation filter in integrated circuit device.
  27. Langhammer, Martin, Implementing division in a programmable integrated circuit device.
  28. Langhammer, Martin, Implementing large multipliers in a programmable integrated circuit device.
  29. Langhammer, Martin, Implementing mixed-precision floating-point operations in a programmable integrated circuit device.
  30. Langhammer, Martin, Implementing multipliers in a programmable integrated circuit device.
  31. Williams,Kenneth Mark; Johnson,Scott Daniel; McNamara,Bruce Saylors; Wang,Albert RenRui, Instruction set for efficient bit stream and byte stream I/O.
  32. Langhammer, Martin; Tharmalingam, Kumara, Large multiplier for programmable logic device.
  33. Langhammer, Martin; Tharmalingam, Kumara, Large multiplier for programmable logic device.
  34. Langhammer, Martin; Tharmalingam, Kumara, Large multiplier for programmable logic device.
  35. Langhammer, Martin; Tharmalingam, Kumara, Large multiplier for programmable logic device.
  36. Gonzalez,Ricardo E.; Johnson,Scott; Taylor,Derek, Long instruction word processing with instruction extensions.
  37. Langhammer, Martin, Matrix decomposition in an integrated circuit device.
  38. Kurtz, Brian L., Matrix operations in an integrated circuit device.
  39. Langhammer, Martin, Matrix operations in an integrated circuit device.
  40. Mauer, Volker; Demirsoy, Suleyman Sirri, Method for configuring a finite impulse response filter in a programmable logic device.
  41. Streicher, Keone; Langhammer, Martin; Lin, Yi-Wen; Leung, Wai-Bor; Lewis, David; Mauer, Volker; Lui, Henry Y.; Demirsoy, Suleyman Sirri; Yi, Hyun, Modular digital signal processing circuitry with optionally usable, dedicated connections between modules of the circuitry.
  42. Streicher, Keone; Langhammer, Martin; Lin, Yi-Wen; Leung, Wai-Bor; Lewis, David; Mauer, Volker; Lui, Henry Y.; Demirsoy, Suleyman Sirri; Yi, Hyun, Modular digital signal processing circuitry with optionally usable, dedicated connections between modules of the circuitry.
  43. Streicher, Keone; Langhammer, Martin; Lin, Yi-Wen; Leung, Wai-Bor; Lewis, David; Mauer, Volker; Lui, Henry Y.; Demirsoy, Suleyman Sirri; Yi, Hyun, Modular digital signal processing circuitry with optionally usable, dedicated connections between modules of the circuitry.
  44. Langhammer, Martin, Multi-operand floating point operations in a programmable integrated circuit device.
  45. Langhammer, Martin, Multiple-precision processing block in a programmable integrated circuit device.
  46. Choe, Kok Heng; Ngai, Tony K; Lui, Henry Y., Multiplier-accumulator circuitry and methods.
  47. Langhammer, Martin, Normalization of floating point operations in a programmable integrated circuit device.
  48. Langhammer, Martin, Normalization of floating point operations in a programmable integrated circuit device.
  49. Mauer, Volker; Langhammer, Martin, Pipelined systolic finite impulse response filter.
  50. Langhammer, Martin, Polynomial calculations optimized for programmable integrated circuit device structures.
  51. Langhammer, Martin, Programmable device using fixed and configurable logic to implement floating-point rounding.
  52. Langhammer, Martin, Programmable device using fixed and configurable logic to implement recursive trees.
  53. Mauer, Volker; Langhammer, Martin, Programmable device with specialized multiplier blocks.
  54. Arnold, Jeffrey Mark; Banta, Gareld Howard; Johnson, Scott Daniel; Wang, Albert R., Programmable logic configuration for instruction extensions.
  55. Langhammer,Martin, Programmable logic device with routing channels.
  56. Langhammer,Martin, Programmable logic device with routing channels.
  57. Langhammer, Martin, QR decomposition in an integrated circuit device.
  58. Mauer, Volker, QR decomposition in an integrated circuit device.
  59. Langhammer, Martin; Dhanoa, Kulwinder, Solving linear matrices in an integrated circuit device.
  60. Langhammer, Martin, Specialized processing block for implementing floating-point multiplier with subnormal operation support.
  61. Xu, Lei; Mauer, Volker; Perry, Steven, Specialized processing block for programmable integrated circuit device.
  62. Langhammer, Martin; Lee, Kwan Yee Martin; Azgomi, Orang; Streicher, Keone; Lin, Yi-Wen, Specialized processing block for programmable logic device.
  63. Langhammer, Martin; Lee, Kwan Yee Martin; Azgomi, Orang; Streicher, Keone; Pelt, Robert L., Specialized processing block for programmable logic device.
  64. Langhammer, Martin; Lee, Kwan Yee Martin; Nguyen, Triet M.; Streicher, Keone; Azgomi, Orang, Specialized processing block for programmable logic device.
  65. Lee, Kwan Yee Martin; Langhammer, Martin; Lin, Yi-Wen; Nguyen, Triet M., Specialized processing block for programmable logic device.
  66. Lee, Kwan Yee Martin; Langhammer, Martin; Nguyen, Triet M.; Lin, Yi-Wen, Specialized processing block for programmable logic device.
  67. Langhammer, Martin, Specialized processing block with fixed- and floating-point structures.
  68. Rupp, Charle' R., System, apparatus and method for data path routing configurable to perform dynamic bit permutations.
  69. Rupp,Charle' R., System, apparatus and method for data path routing configurable to perform dynamic bit permutations.
  70. Rupp, Charle' R.; Arnold, Jeffrey M., System, apparatus and method for implementing multifunctional memory in reconfigurable data path processing.
  71. Gonzalez, Ricardo E.; Wang, Albert R., Systems and methods for selecting input/output configuration in an integrated circuit.
  72. Gonzalez, Ricardo E.; Wang, Albert R.; Banta, Gareld Howard, Systems and methods for software extensible multi-processing.
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