초록 ▼

A system includes a generator component that determines a plurality of portions that comprise an entirety of error-indicating acknowledgement information. The system includes a generator component that cycles through the plurality of portions that comprise the entirety of the error-indicating acknow

A system includes a generator component that determines a plurality of portions that comprise an entirety of error-indicating acknowledgement information. The system includes a generator component that cycles through the plurality of portions that comprise the entirety of the error-indicating acknowledgement information to send the error-indicating acknowledgement information.

대표청구항 ▼

A system includes a generator component that determines a plurality of portions that comprise an entirety of error-indicating acknowledgement information. The system includes a generator component that cycles through the plurality of portions that comprise the entirety of the error-indicating acknow

A system includes a generator component that determines a plurality of portions that comprise an entirety of error-indicating acknowledgement information. The system includes a generator component that cycles through the plurality of portions that comprise the entirety of the error-indicating acknowledgement information to send the error-indicating acknowledgement information. mpression test data," Proc. VLSI Test Symposium, pp. 62-69, 1998. K. Kim, D.S. Ha, J.G. Tront, "On using signature registers as pseudorandon pattern generators in built-in self testing," IEEE Trans. CAD of IC, vol. CAD-7, No. 8, 1988, pp. 919-928. G. Mrugalski, J. Rajski, J. Tyszer, "Synthesis of pattern generators based on cellular automata with phase shifters," Proc. Int. Test Conf., pp. 368-377, 1999. R. Kapur, S. Patil, T.J. Snethen, and T.W. Williams, "Design of an efficient weighted random pattern generation system," Proc. ITC., pp. 491-500, 1994. F. Muradali, V.K. Agarwal, and B. Nadeau-Dostie, "A new procedure for weighted random built-in self-test," Proc. ITC., pp. 600-669, 1990. S. Pateras and J. Rajski "Cube contained random patterns and their application to the complete testing of synthesized multi-level circuits," Proc. ITC., pp. 473-482, 1991. J. Rajski, J. Tyszer, "Test responses compaction in accumulators with rotate carry adders," IEEE Transactions CAD of Integrated Circuits and Systems, vol. CAD-12, No. 4, pp. 531-539, 1993. J. Rajski, J. Tyszer, "Accumulator-based compaction of test responses," IEEE Transactions on Comput., vol. C-42, No. 6, pp. 643-650, 1993. N.R. Saxena and E.J. McCluskey, "Analysis of checksums, extended-precision checksums, and cyclic redundancy," IEEE Trans. Comput., vol. C-39, No. 7, pp. 969-975, 1990. N.A. Touba and E.J. McCluskey, "Transformed pseudo-random patterns for BIST," Proc. VLSI Test Symposium, pp. 410-416, 1995. IEEE. N.A. Touba and E.J. McCluskey, "Altering a pseudo-random bit sequence for scan-based BIST," Proc. ITC., pp. 167-175, 1996. K. H. Tsai, S. Hellebrand, J. Rajs