초록 ▼

High quality dielectric layers, e.g., high-k dielectric layers comprised of at least one refractory or lanthanum series transition metal oxide or silicate, for use as gate insulator layers in in-laid metal gate MOS transistors and CMOS devices, are formed by electrolessly plating a metal or metal-ba

High quality dielectric layers, e.g., high-k dielectric layers comprised of at least one refractory or lanthanum series transition metal oxide or silicate, for use as gate insulator layers in in-laid metal gate MOS transistors and CMOS devices, are formed by electrolessly plating a metal or metal-based dielectric precursor layer comprising at least one refractory or lanthanum series transition metal, such as of Zr and/or Hf, on a silicon-based semiconductor substrate and then reacting the precursor layer with oxygen or with oxygen and the Si-based semiconductor substrate to form the at least one metal oxide or silicate. The inventive methodology prevents, or at least substantially reduces, oxygen access to the substrate surface during at least the initial stage(s) of formation of the gate insulator layer, thereby minimizing deleterious formation of oxygen-induced surface states at the semiconductor substrate/gate insulator interface.

대표청구항 ▼

High quality dielectric layers, e.g., high-k dielectric layers comprised of at least one refractory or lanthanum series transition metal oxide or silicate, for use as gate insulator layers in in-laid metal gate MOS transistors and CMOS devices, are formed by electrolessly plating a metal or metal-ba

High quality dielectric layers, e.g., high-k dielectric layers comprised of at least one refractory or lanthanum series transition metal oxide or silicate, for use as gate insulator layers in in-laid metal gate MOS transistors and CMOS devices, are formed by electrolessly plating a metal or metal-based dielectric precursor layer comprising at least one refractory or lanthanum series transition metal, such as of Zr and/or Hf, on a silicon-based semiconductor substrate and then reacting the precursor layer with oxygen or with oxygen and the Si-based semiconductor substrate to form the at least one metal oxide or silicate. The inventive methodology prevents, or at least substantially reduces, oxygen access to the substrate surface during at least the initial stage(s) of formation of the gate insulator layer, thereby minimizing deleterious formation of oxygen-induced surface states at the semiconductor substrate/gate insulator interface. 1. A semiconductor dual damascene etching process in a confined plasma chamber being in a clean mode and including a confinement ring and an anti-etching upper electrode plate, said semiconductor dual damascene etching process comprising the steps of: providing a wafer having a via hole, an intermetal dielectric layer, a metal line, a barrier layer and a photoresist layer for defining a trench pattern, said wafer being placed in a space enclosed by said confinement ring and said upper electrode plate; etching said intermetal dielectric layer to form said trench; stripping said photoresist layer and cleaning said confined plasma chamber simultaneously by plasma; and etching said barrier layer to have said via hole in contact with said metal line beneath said barrier layer. 2. The semiconductor dual damascene etching process of claim 1, further comprising a step of etching a hard mask. 3. The semiconductor dual damascene etching process of claim 1, wherein said photoresist layer is a silicon-containing photoresist. 4. The semiconductor dual damascene etching process of claim 1, further comprising a clean step to remove a residual polymer in said confined plasma chamber after said wafer is away from said confined plasma chamber. 5. The semiconductor dual damascene etching process of claim 4, wherein said clean step is to use oxygen plasma. 6. The semiconductor dual damascene etching process of claim 4, wherein said clean step uses mixed plasma containing oxygen and CF4. 7. The semiconductor dual damascene etching process of claim 1, wherein said confinement ring is made of quartz. 8. The semiconductor dual damascene etching process of claim 1, wherein said upper electrode plate is made of silicon. 9. The semiconductor dual damascene etching process of claim 1, wherein said intermetal dielectric layer is etched by C--F based plasma. 10. The semiconductor dual damascene etching process of claim 1, wherein said plasma is oxygen plasma. 11. The semiconductor dual damascene etching process of claim 1, wherein said plasma is mixed plasma containing oxygen and CF4. 12. The semiconductor dual damascene etching process of claim 1, wherein said barrier layer is etched by CF4based mixed plasma. 13. A semiconductor dual damascene etching process in a confined plasma chamber being in a clean mode and including a confinement ring and an anti-etching upper electrode plate, said semiconductor dual damascene etching process comprising the steps of: providing a wafer having a trench, an intermetal dielectric layer, a metal line, a barrier layer and a photoresist layer for defining a via hole pattern, said wafer being placed in a space enclosed by said confinement ring and said upper electrode plate; etching said intermetal dielectric layer to form said via hole; stripping said photoresist layer and cleaning said confined plasma chamber simultaneously by plasma; and etching said barrier layer to have said via hole in contact with said metal line beneath said barrier layer. 14. The semiconductor dual damascene etching process of claim 13, further comprising a clean step to remove a residual polymer in said confined plasma chamber after said wafer is away from said confined plasma chamber. 15. The semiconductor dual damascene etching process of claim 14, wherein said clean step is to use oxygen plasma. 16. A semiconductor dual damascene etching process in a confined plasma chamber being in clean mode and including a confinement ring and an anti-etching upper electrode plate, said semiconductor dual damascene etching process comprises the steps of: providing a wafer having an intermetal dielectric layer, a metal line, a barrier layer and a photoresist layer for defining a trench pattern, said wafer being placed in a space enclosed by said confinement ring and said upper electrode plate; etching said intermetal dielectric layer to form said trench and said via hole; stripping said photoresist layer