IPC분류정보
국가/구분 |
United States(US) Patent
등록
|
국제특허분류(IPC7판) |
|
출원번호 |
US-0963478
(2001-09-27)
|
우선권정보 |
JP-0297987 (2000-09-29) |
발명자
/ 주소 |
- Nishimura, Hirofumi
- Araki, Keiji
|
출원인 / 주소 |
|
대리인 / 주소 |
|
인용정보 |
피인용 횟수 :
41 인용 특허 :
10 |
초록
▼
In the case that an engine is operated in a state where an in-cylinder air/fuel ratio is lean in a stratified combustion region and a fuel cut control is performed under a predetermined condition, when catalysts are in a low temperature state where a purification performance is deteriorated or when
In the case that an engine is operated in a state where an in-cylinder air/fuel ratio is lean in a stratified combustion region and a fuel cut control is performed under a predetermined condition, when catalysts are in a low temperature state where a purification performance is deteriorated or when a NOx absorptive amount of the lean NOx catalyst, a control procedure for exhaust air/fuel state at a recovery timing from the fuel cut control so that a driving sensation is improved while maintaining the exhaust purification performance by the catalysts. When the fuel cut control is terminated and the engine shifts into the stratified combustion region, if a catalyst temperature is at or below a set temperature or a NOx absorptive amount is at or above a set amount, the in-cylinder air/fuel ratio of the engine is correctively enriched and the exhaust air/fuel state is enriched.
대표청구항
▼
In the case that an engine is operated in a state where an in-cylinder air/fuel ratio is lean in a stratified combustion region and a fuel cut control is performed under a predetermined condition, when catalysts are in a low temperature state where a purification performance is deteriorated or when
In the case that an engine is operated in a state where an in-cylinder air/fuel ratio is lean in a stratified combustion region and a fuel cut control is performed under a predetermined condition, when catalysts are in a low temperature state where a purification performance is deteriorated or when a NOx absorptive amount of the lean NOx catalyst, a control procedure for exhaust air/fuel state at a recovery timing from the fuel cut control so that a driving sensation is improved while maintaining the exhaust purification performance by the catalysts. When the fuel cut control is terminated and the engine shifts into the stratified combustion region, if a catalyst temperature is at or below a set temperature or a NOx absorptive amount is at or above a set amount, the in-cylinder air/fuel ratio of the engine is correctively enriched and the exhaust air/fuel state is enriched. st logic circuit of the sixth decoder. 8. A semiconductor memory device according to claim 7, wherein an output terminal of the first logic circuit of the seventh decoder crosses an output terminal of the first logic circuit of the eighth decoder. 9. A semiconductor memory device according to claim 4, wherein the first to eighth decoders each has a first logic circuit and a second logic circuit connected in series to the first logic circuit, and an input terminal of the first logic circuit of the fifth decoder crosses an input terminal of the first logic circuit of the sixth decoder. 10. A semiconductor memory device according to claim 9, wherein an input terminal of the first logic circuit of the seventh decoder crosses an input terminal of the first logic circuit of the eighth decoder. 11. A semiconductor memory device according to claim 1, wherein the second, third, sixth and seventh decoders are included in a first decoder section, the first, fourth, fifth and eighth decoders are included in a second decoder section, and the memory cell array is interposed between the first and second decoder sections. 12. A semiconductor memory device according to claim 1, wherein the first and fifth decoders have a wire and a contact in common. 13. A semiconductor memory device according to claim 11, wherein the first and fifth decoders have a wire and a contact in common. 14. A semiconductor memory device according to claim 13, wherein the first to eighth decoders each has a first logic circuit and a second logic circuit connected in series to the first logic circuit, and an output terminal of the second logic circuit of the second decoder crosses an output terminal of the second logic circuit of the third decoder. 15. A semiconductor memory device according to claim 14, wherein an output terminal of the second logic circuit of the first decoder crosses an output terminal of the second logic circuit of the fourth decoder. 16. A semiconductor memory device according to claim 13, wherein the first to eighth decoders each has a first logic circuit and a second logic circuit connected in series to the first logic circuit, and an output terminal of the first logic circuit of the second decoder crosses an output terminal of the first logic circuit of the third decoder. 17. A semiconductor memory device according to claim 16, wherein an output terminal of the first logic circuit of the first decoder crosses an output terminal of the first logic circuit of the fourth decoder. 18. A semiconductor memory device according to claim 13, wherein the first to eighth decoders each has a first logic circuit and a second logic circuit connected in series to the first logic circuit, and an input terminal of the first logic circuit of the second decoder crosses an input terminal of the first logic circuit of the third decoder. 19. A semiconductor memory device according to claim 18, wherein an input terminal of the first logic circuit of the first decoder crosses an input terminal of the first logic circuit of the fourth decoder. 20. A semiconductor memory device comprising: a memory cell array including a plurality of memory cells arranged in rows and columns; a plurality of word lines connected to the plurality of memory cells of one row, respectively, the plurality of word lines including first to eighth word lines arranged in order in the memory cell array, and first to eighth decoders that select the first to eighth word lines, respectively, wherein the third decoder and the seventh decoder have a wire and a contact in common. 21. A semiconductor memory device according to claim 20, wherein the second, third, sixth and seventh decoders are included in a first decoder section, the first, fourth, fifth and eighth decoders are included in a second decoder section, and the memory cell array is interposed between the first and second decoder sections. 22. A semiconductor memory device according to claim 20, wherein the first and fifth decoders have a wire and a contact in common. 23. A semiconductor memory device according to claim 21, wherein the first and fifth decoders have a wire and a contact in common. 24. A semiconductor memory device according to claim 23, wherein the first to eighth decoders each has a first logic circuit and a second logic circuit connected in series to the first logic circuit, and an output terminal of the second logic circuit of the sixth decoder crosses an output terminal of the second logic circuit of the seventh decoder. 25. A semiconductor memory device according to claim 24, wherein an output terminal of the second logic circuit of the first decoder crosses an output terminal of the second logic circuit of the fourth decoder. 26. A semiconductor memory device according to claim 23, wherein the first to eighth decoders each has a first logic circuit and a second logic circuit connected in series to the first logic circuit, and an output terminal of the first logic circuit of the sixth decoder crosses an output terminal of the first logic circuit of the seventh decoder. 27. A semiconductor memory device according to claim 26, wherein an output terminal of the first logic circuit of the first decoder crosses an output terminal of the first logic circuit of the fourth decoder. 28. A semiconductor memory device according to claim 23, wherein the first to eighth decoders each has a first logic circuit and a second logic circuit connected in series to the first logic circuit, and an input terminal of the first logic circuit of the sixth decoder crosses an input terminal of the first logic circuit of the seventh decoder. 29. A semiconductor memory device according to claim 28, wherein an input terminal of the first logic circuit of the first decoder crosses an input terminal of the first logic circuit of the fourth decoder. 30. A semiconductor memory device comprising: a memory cell array including a plurality of memory cells arranged in rows and columns; a plurality of word lines connected to the plurality of memory cells of one row, respectively, and arranged in order in the memory cell array; and decoders that select the plurality of word lines, respectively, wherein the decoders include a pair of decoders having a wire and a contact in common, and (2N-1) (N: natural number) word lines are interposed between word lines driven by the pair of decoders. 31. A semiconductor memory device according to claim 30, wherein a word line driven by a decoder included in the pair of decoders crosses another word line. 32. A semiconductor memory device according to claim 30, wherein the decoders each has a first logic circuit and a second logic circuit connected in series to the first logic circuit, and an output terminal of the second logic circuit of a decoder included in the pair of decoders crosses an output terminal of the second logic circuit of another decoder. 33. A semiconductor memory device according to claim 30, wherein the decoders each has a first logic circuit and a second logic circuit connected in series to the first logic circuit, and an output terminal of the first logic circuit of a decoder included in the pair of decoders crosses an output terminal of the first logic circuit of another decoder. 34. A semiconductor memory device according to claim 30, wherein the decoders each has a fist logic circuit and a second logic circuit connected in series to he first logic circuit, and an input terminal of the first logic circuit of a decoder included in the pair of decoders crosses an input terminal of the first logic circuit of another decoder. usly scrolling message of medical information at a preselected time; a notification means for signaling a medical event at a preselected time, by scrolling said medical event on said display means, and activating an alarm means; a reminder mode activation means for activating a reminder mode and deactivating said notification means, in which said reminder mode includes a reminder alarm means which activates at periodic intervals until said reminder mode is deactivated, and in which a medical event is displayed in said display means; a confirmation button which deactivates said reminder mode and said notification means when activated, and which a user activates when said medical event has been responded to; and a watch face with only a single readout button, which accesses a first unit of stored medical information and displays said first unit of stored medical information upon said display means when said single readout button is depressed once, and in which each subsequent depression of said single readout button results in a display of a subsequent unit of stored medical information, until all units of medical information have been displayed. 2. The device of claim 1 wherein additional depression of said single readout button after all units of medical information have been displayed causes display of said first unit of stored medical information, and a repetition of displayed units of medical information is available. 3. The medical information appliance of claim 1 in which said reminder mode sequentially displays multiple medical events if more than one medical event has occurred without activation of said confirmation button, and which allows the selective deactivation of chosen medical events in said reminder mode by depressing said confirmation button during display of said selected medical event in said reminder mode. 4. The medical information appliance of claim 1 in which said display means is comprised of a pixel field in which characters are formed. 5. The medical information appliance of claim 4 in which said display means is comprised of two rows of pixel fields, with a first display row positioned above a second display row. 6. The medical information appliance of claim 4 in which said display means presents a right to left scrolling of characters. 7. The medical information appliance of claim 1 which further comprises a means of recording a time when said confirmation button is depressed for a history of times medical events were taken confirmed. 8. The medical information appliance of claim 1 in which said medical information appliance is in the form of a watch worn by a user. 9. The medical information appliance of claim 8 in which said medical information appliance is in the form of a wrist watch worn by a user. 10. The medical information appliance of claim 1 in which said medical information appliance is in the form of a hand held computer. 11. The medical information appliance of claim 1 which further comprises a means to exchange information between said medical information appliance with computer means. 12. The medical information appliance of claim 1 in which said alarm means is a sound emitted by said medical information appliance. 13. The medical information appliance of claim 1 in which said alarm means is a vibration emitted by said medical information appliance. 14. The medical information appliance of claim 1 in which said memory means comprises eleven fields for recording medical information, and each field holds 36 characters of information. 15. The medical information appliance of claim 6 in which medical information concerning a medical event scrolls across said first display row when a medical event is indicated, and simultaneously said alarm means is activated. 16. The medical information appliance of claim 14 in which said second display row displays time when a medical event is indicated. 17. The medical information appliance of claim 13 in which said reminder activation means is a
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