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A method for forming dual-damascene type conducting interconnects with non-metallic barriers that protect said interconnects from fluorine out-diffusion from surrounding low-k, fluorinated dielectric materials. One embodiment of the method is particularly suited for forming such interconnects in mic

A method for forming dual-damascene type conducting interconnects with non-metallic barriers that protect said interconnects from fluorine out-diffusion from surrounding low-k, fluorinated dielectric materials. One embodiment of the method is particularly suited for forming such interconnects in microelectronics fabrications of the sub 0.15 micron generation.

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A method for forming dual-damascene type conducting interconnects with non-metallic barriers that protect said interconnects from fluorine out-diffusion from surrounding low-k, fluorinated dielectric materials. One embodiment of the method is particularly suited for forming such interconnects in mic

A method for forming dual-damascene type conducting interconnects with non-metallic barriers that protect said interconnects from fluorine out-diffusion from surrounding low-k, fluorinated dielectric materials. One embodiment of the method is particularly suited for forming such interconnects in microelectronics fabrications of the sub 0.15 micron generation. cted from the group consisting of Cu+(BTA-), Cu++(BTA-)2,and mixtures thereof. 20. The method recited in claim 8, wherein the electrical interconnect layer comprises an electrically conductive material selected from the group consisting of an electrically conductive epoxy, an electrically conductive solder material, and mixtures thereof. 21. The method recited in claim 8, wherein the electrical interconnect layer comprises a base resin material having electrically conducting particles selected from the group consisting of silver particles, nickel particles, and mixtures thereof. 22. The method as recited in claim 8, wherein the organometallic layer has a thickness less than about 30 Angstroms. 23. A method for forming a semiconductor device on a semiconductor substrate, the method comprising: forming over the semiconductor substrate a first metal layer that comprises a first metal; forming a first diffusion barrier layer on the first metal layer; forming a second diffusion barrier layer upon and in contact with the semiconductor substrate, wherein: the first metal layer is upon and in contact with the second diffusion barrier layer; and the second diffusion barrier layer prevents diffusion of at least one of the semiconductor substrate and the first metal layer therethrough; forming a second metal layer comprising a second metal and situated on the first diffusion barrier layer, the first diffusion barrier layer preventing diffusion of at least one of the first metal and the second metal therethrough; forming an organometallic layer on the second metal layer; forming an electrical interconnect layer on the organometallic layer; and forming a third metal layer on the electrical interconnect layer. 24. The method recited in claim 23, wherein the organometallic layer comprises a metal azole complex. 25. The method recited in claim 23, further comprising forming a second substrate on the third metal layer. 26. The method recited in claim 23, wherein the third metal layer comprises an electrically conducting metal selected from the group consisting of aluminum, copper, an aluminum copper alloy, and mixtures thereof. 27. The method recited in claim 23, wherein the second diffusion barrier layer comprises titanium, the first metal layer comprises a material selected from the group consisting of aluminum, copper, an aluminum copper alloy, and mixtures thereof, and the semiconductor substrate comprises a silicon-containing material. 28. A method for forming a semiconductor device on a semiconductor substrate, the method comprising: forming a first diffusion barrier layer upon and in contact with the semiconductor substrate; forming a first metal layer, comprising aluminum, upon and in contact with the first diffusion barrier layer, wherein said first diffusion barrier layer prevents diffusion of at least one of the semiconductor substrate and the first metal layer therethrough; forming a second diffusion barrier layer on the first metal layer; forming a second metal layer on the second diffusion barrier layer comprising copper, the second diffusion barrier layer preventing diffusion of at least one of aluminum and copper therethrough; forming an organometallic layer on the second metal layer; and forming on the organometallic layer an electrical interconnect layer comprising an electrically conductive material selected from the group consisting of an electrically conductive epoxy, an electrically conductive solder material, and mixtures thereof. 29. The method recited in claim 28, wherein the organometallic layer comprises an organic complex of copper. 30. The method recited in claim 28, wherein the second diffusion barrier layer comprises a metal selected from the group consisting of nickel, titanium tungsten, titanium nitride, and mixtures thereof. 31. The method recited in claim 28, wherein: the first diffusion barrier layer comprises titanium; the f