초록 ▼

A hardware search engine facility is provided to allow CPU search and update of a Forwarding Table CAM under the control of software running on the CPU. The hardware search engine provides one or more comparand-mask pairs which allow for a match, exclusion or magnitude comparison on specific entry v

A hardware search engine facility is provided to allow CPU search and update of a Forwarding Table CAM under the control of software running on the CPU. The hardware search engine provides one or more comparand-mask pairs which allow for a match, exclusion or magnitude comparison on specific entry values and/or the option to ignore or "don't care" certain bits of the entry. Control registers may be set in software to specify a start address and stop address in the CAM for the search. An indication of valid or invalid entries may be provided as well. Once the search is initiated by software, the search engine will read the entries sequentially starting from the programmed start address. It will perform a compare using the comparand-mask pair and attempt to identify a match. The locations in the CAM which match the search criteria may be put into a CPU-accessible memory. If the memory fills up before it can be read by the software, the search may be halted until the memory is emptied. A programmable action may instead, or in addition, be set to take place in the event of a match. Such programmable actions may include, but are not limited to, marking the entry, deleting the entry, change status bits corresponding to the entry, rewriting some of the entry, and the like.

대표청구항 ▼

A hardware search engine facility is provided to allow CPU search and update of a Forwarding Table CAM under the control of software running on the CPU. The hardware search engine provides one or more comparand-mask pairs which allow for a match, exclusion or magnitude comparison on specific entry v

A hardware search engine facility is provided to allow CPU search and update of a Forwarding Table CAM under the control of software running on the CPU. The hardware search engine provides one or more comparand-mask pairs which allow for a match, exclusion or magnitude comparison on specific entry values and/or the option to ignore or "don't care" certain bits of the entry. Control registers may be set in software to specify a start address and stop address in the CAM for the search. An indication of valid or invalid entries may be provided as well. Once the search is initiated by software, the search engine will read the entries sequentially starting from the programmed start address. It will perform a compare using the comparand-mask pair and attempt to identify a match. The locations in the CAM which match the search criteria may be put into a CPU-accessible memory. If the memory fills up before it can be read by the software, the search may be halted until the memory is emptied. A programmable action may instead, or in addition, be set to take place in the event of a match. Such programmable actions may include, but are not limited to, marking the entry, deleting the entry, change status bits corresponding to the entry, rewriting some of the entry, and the like. . 31. The memory device of claim 30, wherein the memory device comprises SDRAM memory. 32. The memory device of claim 30, wherein the memory device comprises DDR memory. 33. The memory device of claim 28, wherein the data interface further comprises a data latch coupled to the SMD clock recovery and skew adjustment circuit. 34. The memory device of claim 28, wherein the data interface further comprises a DQS strobe circuit coupled to the SMD clock recovery and skew adjustment circuit. 35. A DDR memory device interface circuit comprising: a data interface; a DQS signal interface; a data latch coupled to the data interface; and an SMD clock recovery and skew adjustment circuit coupled to the data latch and the DQS signal interface, wherein the SMD clock recovery and skew adjustment circuit comprises, a clock source, a delay segment coupled to the clock source, a data path model coupled to the delay segment, a forward delay line coupled to the data path model, an SMD control circuit coupled to the forward delay line and coupled to the clock source, and a backward delay line coupled to the SMD control circuit and coupled to the delay segment. 36. The DDR memory device interface circuit of claim 35, wherein the DDR memory device interface circuit is