초록 ▼

A silicon-germanium base capable of use in heterojunction bipolar transistor includes a silicon substrate having a mesa surrounded by a trench. The mesa has a top surface and a silicon-germanium layer is disposed only on the top surface of the mesa. In addition, a heterojunction bipolar transistor i

A silicon-germanium base capable of use in heterojunction bipolar transistor includes a silicon substrate having a mesa surrounded by a trench. The mesa has a top surface and a silicon-germanium layer is disposed only on the top surface of the mesa. In addition, a heterojunction bipolar transistor includes the silicon-germanium base as described.

대표청구항 ▼

A silicon-germanium base capable of use in heterojunction bipolar transistor includes a silicon substrate having a mesa surrounded by a trench. The mesa has a top surface and a silicon-germanium layer is disposed only on the top surface of the mesa. In addition, a heterojunction bipolar transistor i

A silicon-germanium base capable of use in heterojunction bipolar transistor includes a silicon substrate having a mesa surrounded by a trench. The mesa has a top surface and a silicon-germanium layer is disposed only on the top surface of the mesa. In addition, a heterojunction bipolar transistor includes the silicon-germanium base as described. rt substrate; a second supporting substrate facing the semiconductor layer formed on the insulating layer on the first supporting substrate; and a liquid crystal disposed between the first supporting substrate and the second supporting substrate, and driven by transistor elements in the semiconductor layer. 9. An electronic equipment, comprising: a light source; the electro-optical device according to claim 8 that modulates light incident on the light source in response to image information; and a projection device that projects the light modulated by the electro-optical device. 10. A semiconductor gate array, comprising: a supporting substrate having insulation at least at a surface thereof; a semiconductor layer formed on the surface of the supporting substrate; a plurality of transistors formed in the semiconductor layer, each of the transistors comprising a channel region of a first conductive type formed on the surface of the supporting substrate, a source region and a drain region of a second conductive type formed on the surface of the supporting substrate so as to sandwich the channel region, an insulating layer formed on the channel region, and an electrode formed on the insulating layer; a first semiconductor region provided on the surface of the supporting substrate at least at one end in a channel width direction along both of the source region and the drain region; a second semiconductor region of the first conductive type provided on the surface of the supporting substrate so as to sandwich the first semiconductor region by the source region and the drain region along the first semiconductor region, the second semiconductor region having an impurity concentration which is higher than that in the channel region, and the first semiconductor region having an impurity concentration which is lower than that in the source region and the drain region and is lower than that in the second semiconductor region; and an LDD region of the second conductive type formed between the channel region and the source region and between the channel region and drain region, the first semiconductor region of each transistor being a semiconductor of the second conductive type and having an impurity concentration which is the same as that in the LDD region. 11. The semiconductor gate array according to claim 10, the first semiconductor region of each transistor being a semiconductor of the second conductive type, and having an impurity concentration which is lower than that in the source region and the drain region. 12. A semiconductor gate array according to claim 10, the supporting substrate having insulation at least at a surface thereof comprising a base substrate and an insulating layer formed on the base substrate. 13. The semiconductor gate array according to claim 12, the base substrate comprising single-crystal silicon. 14. The semiconductor gate array according to claim 12, the base substrate comprising quartz, and the semiconductor layer formed on the insulating layer of the supporting substrate comprising single-crystal silicon. 15. The semiconductor gate array according to claim 12, the base substrate comprising quartz, and the semiconductor layer formed on the insulating layer of the supporting substrate comprising polycrystalline silicon. 16. The semiconductor gate array according to claim 12, the base substrate comprising glass. 17. An electro-optical device, comprising: the supporting substrate constituting the semiconductor gate array according to claim 15 as a first supporting substrate; a second supporting substrate facing the semiconductor layer formed on the insulating layer on the first supporting substrate; and a liquid crystal disposed between the first supporting substrate and the second supporting substrate, and driven by transistor elements in the semiconductor layer. 18. An electronic equipment, comprising: a light source; the electro-optical device according to claim 17 that mo