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An error-correcting partial latch stage includes a first pass gate having an input for receiving a data input signal, an output, and a control node for receiving a control signal, a second pass gate having an input coupled to the output of the first pass gate, an output for providing a data output s

An error-correcting partial latch stage includes a first pass gate having an input for receiving a data input signal, an output, and a control node for receiving a control signal, a second pass gate having an input coupled to the output of the first pass gate, an output for providing a data output signal, and a control node for receiving the control signal, an inverter having an input coupled to the output of the first pass gate and an output; and a correcting inverter stage having a first input coupled to the output of the inverter, and second and third inputs for receiving voting signals from adjacent error-correcting latch stages, and an output coupled to the output of the second pass gate. A full latch stage includes three interconnected partial latch stages. The full latch stage has a high degree of immunity from SEU events and from on-chip noise coupling.

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An error-correcting partial latch stage includes a first pass gate having an input for receiving a data input signal, an output, and a control node for receiving a control signal, a second pass gate having an input coupled to the output of the first pass gate, an output for providing a data output s

An error-correcting partial latch stage includes a first pass gate having an input for receiving a data input signal, an output, and a control node for receiving a control signal, a second pass gate having an input coupled to the output of the first pass gate, an output for providing a data output signal, and a control node for receiving the control signal, an inverter having an input coupled to the output of the first pass gate and an output; and a correcting inverter stage having a first input coupled to the output of the inverter, and second and third inputs for receiving voting signals from adjacent error-correcting latch stages, and an output coupled to the output of the second pass gate. A full latch stage includes three interconnected partial latch stages. The full latch stage has a high degree of immunity from SEU events and from on-chip noise coupling. ut mode in response to the input signal having a voltage less than a voltage threshold, the well pulling circuit further having a second drive transistor coupled between the bias terminal and the I/O node to couple the bias terminal to the I/O node during the input mode in response to the input signal having a voltage greater than the voltage threshold, and a PMOS drive circuit having a drive terminal coupled to the gate of the PMOS pull-up transistor and further coupled to the bias terminal through a balance switch to couple the body and gate terminals of the pull-up transistor during the input mode. 2. The I/O buffer of claim 1 wherein the pull-down transistor comprises an NMOS transistor. 3. The I/O buffer of claim 1 wherein the voltage threshold is approximately equal to the voltage of the first supply voltage. 4. The I/O buffer of claim 1 wherein the PMOS pull-up transistor is formed in an n-well. 5. An input/output (I/O)buffer coupled between first and second supply voltages for receiving an input signal during an input mode and for providing an output signal during an output mode, the I/O buffer comprising: a driver circuit having pull-up and pull-down transistors coupled in series and an I/O node disposed therebetween to receive the input signal, the pull up transistor having gate and body terminals; and a pull-up transistor bias circuit having a bias terminal coupled to the gate and body terminals of the pull-up transistor, a well pulling circuit having a first drive transistor coupled between the first supply voltage and the bias terminal to couple the bias terminal to the first supply voltage during the input mode in response to the input signal having a voltage less than a voltage threshold, the well pulling circuit further having a second drive transistor coupled between the bias terminal and the I/O node to couple the bias terminal to the I/O node in response to the input signal having a voltage greater than the voltage threshold, and a pull-up transistor drive circuit having a drive terminal coupled to the gate of the pull-up transistor and further coupled to the bias terminal through a balance switch to couple the body and gate terminals of the pull-up transistor during the input mode. 6. The I/O buffer of claim 5 wherein the pull-up transistor comprises a PMOS transistor. 7. The I/O buffer of claim 6 wherein the PMOS pull-up transistor is formed in an n-well. 8. The I/O buffer of claim 5 wherein the pull-down transistor comprises an NMOS transistor. 9. The I/O buffer of claim 5 wherein the voltage threshold is approximately equal to the voltage of the first supply voltage. 10. The I/O buffer of claim 5 wherein the well pulling circuit comprises: a pass gate having an input terminal coupled to the I/O node, and further having an output terminal and p- and n-gate terminals, the pass gate coupling a signal applied to the input terminal to the output terminal in response to receiving activation signals on the p- and n-gate terminals; a p-pass gate bias circuit having a p-gate activation terminal coupled to the p-gate terminal of the pass gate and an activation terminal coupled to the output terminal of the pass gate, and further having a second source activation terminal, the p-pass gate bias circuit providing an activation signal on the second source activation terminal responsive to signal provided on the output terminal of the pass gate; a well switch having a bias output coupled to the bias terminal, a first activation terminal coupled to the output terminal of the pass gate, a second activation terminal coupled to the second source activation terminal of the p-pass gate bias circuit, a first source terminal coupled to the first supply voltage and a second source terminal coupled to the I/O node, the well switch coupling the I/O node to the bias output responsive to an activation signal received on the second activation terminal and coupling the first voltage source to the bias output responsiv