초록 ▼

A clock distribution network is provided which includes variable-delay element. The variable-delay element consists of an inverter and a digitally adjustable resistor. The digitally adjustable resistor includes a plurality of transistors provided in plurality of rows and a plurality of columns. The

A clock distribution network is provided which includes variable-delay element. The variable-delay element consists of an inverter and a digitally adjustable resistor. The digitally adjustable resistor includes a plurality of transistors provided in plurality of rows and a plurality of columns. The variable-delay element functions logically equivalent to the inverter in which the delay is varied in accordance with the variance in resistance of the digitally adjustable resistor.

대표청구항 ▼

1. A method of selecting a control bit combination, comprising: determining a minimum value and a maximum value for a range of resistance values for a plurality of legal control bit combinations; approximating a minimum resistance value and a maximum resistance value of a control bit combination

1. A method of selecting a control bit combination, comprising: determining a minimum value and a maximum value for a range of resistance values for a plurality of legal control bit combinations; approximating a minimum resistance value and a maximum resistance value of a control bit combination from the plurality of legal control bit combinations for a plurality of fabrication variations; selecting a desired resistance value within the range between the approximated minimum resistance value and the approximated maximum resistance value; selecting the control bit combination based on the approximated minimum resistance value, the approximated maximum resistance value and the desired resistance value; and determining a worst-case resistance deviation from the desired resistance value. 2. The method of claim 1, determining the worst-case resistance deviation comprising determining a maximum difference between a distance between the approximated minimum resistance value and the desired resistance value, and a distance between the approximated maximum resistance value and the desired resistance value. 3. The method of claim 2, the control bit combination being selected when the maximum difference between a distance between the approximated minimum resistance value and the desired resistance value, and a distance between the approximated maximum resistance value and the desired resistance value, is minimum. 4. The method of claim 1, wherein the plurality of legal control bit combinations provide resistance values that are evenly distributed between the minimum value and the maximum value for the range of resistance values. 5. The method of claim 1, wherein the fabrication variations are random. 6. An apparatus comprising: a variable delay element; and a processing element, coupled to the variable delay element, to determine a minimum value and a maximum value for a range of resistance values for a plurality of legal control bit combinations provided to the variable delay element, approximate a minimum resistance value and a maximum resistance value of a control bit combination from the plurality of legal control bit combinations for a plurality of fabrication variations in the variable delay element, select a desired resistance value within the range between the approximated minimum resistance value and the approximated maximum resistance value, select the control bit combination based on the approximated minimum resistance value, the approximated maximum resistance value and the desired resistance value, and determine a worst-case resistance deviation from the desired resistance value. 7. The apparatus of claim 6, wherein the variable delay element includes an inverter and a digitally adjustable resistor. 8. The apparatus of claim 7, wherein the inverter is to invert an input signal. 9. The apparatus of claim 7, wherein the digitally adjustable resistor comprises a plurality of transistors in a plurality of columns and a plurality of rows. 10. The apparatus of claim 6, further comprising a controller to provide the plurality of legal control bit combinations to the variable delay element, the control bit combinations being selected such that resistance values are evenly distributed between the minimum and the maximum resistance values.