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Synthetic aperture radar (SAR) data (118) of a target (108) is collected (12) over a substantially circular arc (128), wherein a.chord (130) of the arc (128) establishes (20) a radar aperture (102) having a substantially perpendicular construct baseline (104) through the target (108). The radar aper

Synthetic aperture radar (SAR) data (118) of a target (108) is collected (12) over a substantially circular arc (128), wherein a.chord (130) of the arc (128) establishes (20) a radar aperture (102) having a substantially perpendicular construct baseline (104) through the target (108). The radar aperture (102) is partitioned (26) into first and second partial apertures (120) having substantially the construct baseline (104). First and second points (150) substantially vertically coincident with the construct baseline (104) are then determined (38) at means (152) of the first and second partial apertures (120), and first and second vectors (106) from the target (108) are established (40) by the first and second points (150), respectively. First and second portions (148) of the SAR data (118) are accumulated (32) over the first and second partial apertures (120), respectively, and first and second vector complex image data (164) of the target (108) is derived (54) in response thereto. The first and second vector complex image data (164) is then interferogrammetrically integrated (80) and the topographic data (116) of the target (108) is produced (14) thereby.

대표청구항 ▼

Synthetic aperture radar (SAR) data (118) of a target (108) is collected (12) over a substantially circular arc (128), wherein a.chord (130) of the arc (128) establishes (20) a radar aperture (102) having a substantially perpendicular construct baseline (104) through the target (108). The radar aper

Synthetic aperture radar (SAR) data (118) of a target (108) is collected (12) over a substantially circular arc (128), wherein a.chord (130) of the arc (128) establishes (20) a radar aperture (102) having a substantially perpendicular construct baseline (104) through the target (108). The radar aperture (102) is partitioned (26) into first and second partial apertures (120) having substantially the construct baseline (104). First and second points (150) substantially vertically coincident with the construct baseline (104) are then determined (38) at means (152) of the first and second partial apertures (120), and first and second vectors (106) from the target (108) are established (40) by the first and second points (150), respectively. First and second portions (148) of the SAR data (118) are accumulated (32) over the first and second partial apertures (120), respectively, and first and second vector complex image data (164) of the target (108) is derived (54) in response thereto. The first and second vector complex image data (164) is then interferogrammetrically integrated (80) and the topographic data (116) of the target (108) is produced (14) thereby. the string of bits; looking up simultaneously a plurality of entries from a plurality of look-up tables using the plurality of indices; and combining the plurality of entries into a first result. 11. A method as in claim 9 wherein the execution unit is one of a plurality of execution units of a Very Long Instruction Word (VLIW) processing engine. 12. A method to decode a variable length encoded bit stream on a processing engine having an instruction cache and local memory, the method comprising: loading a first set of instructions into the instruction cache; loading first data into the local memory; generating second data from the first data by executing the first set of instructions; loading the second data from the local memory into first memory external to the processing engine; loading a second set of instructions into the instruction cache; loading the second data from the first memory into the local memory; and generating third data from the second data by executing the second set of instructions. 13. A method as in claim 12 wherein the first set of instructions comprises instructions for at least one of: a) Macro Block Address Generation (MBAG); and b) Variable Length Decoding (VLD). 14. A method as in claim 12 wherein the second set of instructions comprises instructions for at least one of: a) Variable Length Decoding (VLD); and b) Inverse Discrete Cosine Transformation (IDCT). 15. A method as in claim 12 wherein a second portion of the second data is generated concurrently while a first portion of the second data is loaded from the local memory into the first memory. 16. A method as in claim 12 wherein a first portion of the second data is generated concurrently from a first portion of the first data while a second portion of the first data is loaded from the first memory into the local memory. 17. A method as in claim 12 wherein a first portion of the third data is generated concurrently from a first portion of the second data while a second portion of the second data is loaded from the first memory into the local memory. 18. A method to decode a variable length encoded bit stream on a processing engine having local memory, the method comprising: concurrently loading a first result generated from first data from the local memory into first memory external to the processing engine using a first at least one Direct Memory Access (DMA) channel; while generating a second result from second data in the local memory; and while loading third data into the local memory using a second at least one DMA channel. 19. A method as in claim 18 wherein: the first, second, and third data are Inverse Direct Cosine Transformation (IDCT) coefficients; and the first and second results are decompressed video streams. 20. A method as in claim 18 wherein, after a first portion of the first result is loaded into the first memory, a portion of the second result is stored into a location in the local memory in which the first portion of the first result is stored. 21. A method as in claim 18 wherein: the first, second, and third data are compressed bit streams; and the first and second results are Inverse Direct Cosine Transformation (IDCT) coefficients. 22. A method as in claim 18 wherein: the first and second data are Inverse Direct Cosine Transformation (IDCT) coefficients; the third data is a compressed bit stream; and the first and second results are decompressed video streams. 23. A method as in claim 22 further comprising: concurrently variable length decoding the third data to generate a first set of IDCT coefficients; while loading the second result from the local memory into the first memory using the second at least one DMA channel. 24. A method as in claim 18 wherein the second result is stored into a location in the local memory in which the second data is stored. 25. A method to decode a variable length encoded bit stream, the method comprising: concurrently executin g a first set of instructions in a first processing engine to generate a first result from a first data for a bit stream; while executing a second set of instructions in a second processing engine to generate a second result from a third result; wherein the third result is generated from a second data for the bit stream in the first processing engine after execution of the first set of instructions. 26. A method as in claim 25 wherein the first set of instructions comprises instructions for at least one of: a) Macro Block Address Generation (MBAG); and b) Variable Length Decoding (VLD). 27. A method as in claim 25 wherein the second set of instructions comprises instructions for at least one of: a) Variable Length Decoding (VLD); and b) Inverse Discrete Cosine Transformation (IDCT). 28. A method to decode a variable length encoded bit stream, the method comprising: variable length decoding a bit stream until a condition in a set of conditions is encountered; constructing first data containing information about a segment of the bit stream which has not been decoded; and storing first data in a location in memory, the location being independent on the condition. 29. A method as in claim 28 wherein the set of conditions comprises: a) an end of block condition; and b) an adjust bit stream condition. 30. A method as in claim 28 wherein the first data comprises: a) bits in the segment; b) a bit length of the segment; and c) a type of the segment. 31. A method as in claim 30 wherein the type of the segment is one of: a) incomplete code bits; and b) remaining bits. 32. A machine readable media containing executable computer program instructions which when executed by a digital processing system cause said system to perform a method to decode a variable length encoded bit stream, the method comprising: concurrently processing first data obtained from variable length decoding a first code word in a register; while variable length decoding a second code word in the register. 33. A media as in claim 32 wherein said processing first data comprises: looking up an inverse zigzag index. 34. A media as in claim 33 wherein the inverse zigzag index is for storing an Inverse Direct Cosine Transformation (IDCT) coefficient in a transposed inverse zigzag order. 35. A media as in claim 32 wherein said processing first data comprises: computing an Inverse Direct Cosine Transformation (IDCT) coefficient. 36. A media as in claim 35 wherein said processing first data further comprises: storing the IDCT coefficient in a buffer in a transposed inverse zigzag order. 37. A media as in claim 32 wherein said processing first data comprises: looking up a coefficient for inverse scaling. 38. A media as in claim 32 wherein said processing first data comprises: branching conditionally based on a condition encountered in variable length decoding the first code word. 39. A media as in claim 38 wherein the condition is one of: a) an end of block condition; b) an adjust bit stream condition; and c) an entry not found condition. 40. A media as in claim 32 wherein said variable length decoding the second code word is performed by an execution unit in response to receiving a single instruction. 41. A media as in claim 40 wherein, in response to the single instruction, the execution unit performs a method comprising: receiving a string of bits; generating a plurality of indices using a plurality of segments of bits in the string of bits; looking up simultaneously a plurality of entries from a plurality of look-up tables using the plurality of indices; and combining the plurality of entries into a first result. 42. A media as in claim 40 wherein the execution unit is one of a plurality of execution units of a Very Long Instruction Word (VLIW) processing engine. 43. A machine readable media containing executable computer program instructions which when executed by a digital processing s ystem cause said system to perform a method to decode a variable length encoded bit stream on a processing engine having an instruction cache and local memory, the method comprising: loading a first set of instructions into the instruction cache; loading first data into the local memory; generating second data from the first data by executing the first set of instructions; loading the second data from the local memory into first memory external to the processing engine; loading a second set of instructions into the instruction cache; loading the second data from the first memory into the local memory; and generating third data from the second data by executing the second set of instructions. 44. A media as in claim 43 wherein the first set of instructions comprises instructions for at least one of: a) Macro Block Address Generation (MBAG); and b) Variable Length Decoding (VLD). 45. A media as in claim 43 wherein the second set of instructions comprises instructions for at least one of: a) Variable Length Decoding (VLD); and b) Inverse Discrete Cosine Transformation (IDCT). 46. A media as in claim 43 wherein a second portion of the second data is generated concurrently while a first portion of the second data is loaded from the local memory into the first memory. 47. A media as in claim 43 wherein a first portion of the second data is generated concurrently from a first portion of the first data while a second portion of the first data is loaded from the first memory into the local memory. 48. A media as in claim 43 wherein a first portion of the third data is generated concurrently from a first portion of the second data while a second portion of the second data is loaded from the first memory into the local memory. 49. A machine readable media containing executable computer program instructions which when executed by a digital processing system cause said system to perform a method to decode a variable length encoded bit stream on a processing engine having local memory, the method comprising concurrently loading a first result generated from first data from the local memory into first memory external to the processing engine using a first at least one Direct Memory Access (DMA) channel; while generating a second result from second data in the local memory; and while loading third data into the local memory using a second at least one DMA channel. 50. A media as in claim 49 wherein: the first, second, and third data are Inverse Direct Cosine Transformation (IDCT) coefficients; and the first and second results are decompressed video streams. 51. A media as in claim 49 wherein, after a first portion of the first result is loaded into the first memory, a portion of the second result is stored into a location in the local memory in which the first portion of the first result is stored. 52. A media as in claim 49 wherein: the first, second, and third data are compressed bit streams; and the first and second results are Inverse Direct Cosine Transformation (IDCT) coefficients. 53. A media as in claim 49 wherein: the first and second data are Inverse Direct Cosine Transformation (IDCT) coefficients; the third data is a compressed bit stream; and the first and second results are decompressed video streams. 54. A media as in claim 53 wherein the method further comprises: concurrently variable length decoding the third data to generate a first set of IDCT coefficients; while loading the second result from the local memory into the first memory using the second at least one DMA channel. 55. A media as in claim 49 wherein the second result is stored into a location in the local memory in which the second data is stored. 56. A machine readable media containing executable computer program instructions which when executed by a digital processing system cause said system to perform a method to decode a variable length encoded bit stream, the method comprising: concurrently executing a first set of instructions in a first processing engine to generate a first result from a first data for a bit stream; while executing a second set of instructions in a second processing engine to generate a second result from a third result; wherein the third result is generated from a second data for the bit stream in the first processing engine after execution of the first set of instructions. 57. A media as in claim 56 wherein the first set of instructions comprises instructions for at least one of: a) Macro Block Address Generation (MBAG); and b) Variable Length Decoding (VLD). 58. A media as in claim 56 wherein the second set of instructions comprises instructions for at least one of: a) Variable Length Decoding (VLD); and b) Inverse Discrete Cosine Transformation (IDCT). 59. A machine readable media containing executable computer program instructions which when executed by a digital processing system cause said system to perform a method to decode a variable length encoded bit stream, the method comprising: variable length decoding a bit stream until a condition in a set of conditions is encountered; constructing first data containing information about a segment of the bit stream which has not been decoded; and storing first data in a location in memory, the location being independent on the condition. 60. A media as in claim 59 wherein the set of conditions comprises: a) an end of block condition; and b) an adjust bit stream condition. 61. A media as in claim 59 wherein the first data comprises: a) bits in the segment; b) a bit length of the segment; and c) a type of the segment. 62. A media as in claim 61 wherein the type of the segment is one of: a) incomplete code bits; and b) remaining bits. 63. A variable length encoded bit stream decoder comprising: means for processing first data obtained from variable length decoding a first code word in a register; and means for variable length decoding a second code word in the register; wherein the above means operate concurrently. 64. A decoder as in claim 63 wherein said means for processing first data comprises: means for looking up an inverse zigzag index. 65. A decoder as in claim 64 wherein the inverse zigzag index is for storing an Inverse Direct Cosine Transformation (IDCT) coefficient in a transposed inverse zigzag order. 66. A decoder as in claim 63 wherein said means for processing first data comprises: means for computing an Inverse Direct Cosine Transformation (IDCT) coefficient. 67. A decoder as in claim 66 wherein said means for processing first data further comprises: means for storing the IDCT coefficient in a buffer in a transposed inverse zigzag order. 68. A decoder as in claim 63 wherein said means for processing first data comprises: means for looking up a coefficient for inverse scaling. 69. A decoder as in claim 63 wherein said means for processing first data comprises: means for branching conditionally based on a condition encountered in variable length decoding the first code word. 70. A decoder as in claim 69 wherein the condition is one of: a) an end of block condition; b) an adjust bit stream condition; and c) an entry not found condition. 71. A decoder as in claim 63 wherein said variable length decoding the second code word is performed by an execution unit in response to receiving a single instruction. 72. A decoder as in claim 71 wherein the execution unit comprises: means for receiving a string of bits; means for generating a plurality of indices using a plurality of segments of bits in the string of bits; means for looking up simultaneously a plurality of entries from a plurality of look-up tables using the plurality of indices; and means for combining the plurality of entries into a first result; wherein the above means operate in response to receiving a single instruction. 73. A decoder as in claim 71 wherein the execution unit is one of a plurality o