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Semiconductor chip assembly with interlocked conductive trace 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/44
출원번호 US-0939140 (2001-08-24)
발명자 / 주소
  • Lin, Charles W.C.
대리인 / 주소
    Sigmond, David M.
인용정보 피인용 횟수 : 23  인용 특허 : 135

초록

A semiconductor chip assembly includes a semiconductor chip, a conductive trace, a connection joint, an insulative adhesive and an encapsulant. The conductive trace includes a routing line and a pillar. The routing line extends within and outside a periphery of the chip, and the pillar is disposed o

대표청구항

A semiconductor chip assembly includes a semiconductor chip, a conductive trace, a connection joint, an insulative adhesive and an encapsulant. The conductive trace includes a routing line and a pillar. The routing line extends within and outside a periphery of the chip, and the pillar is disposed o

이 특허에 인용된 특허 (135)

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이 특허를 인용한 특허 (23)

  1. Lin,Charles W. C., Method of making a semiconductor chip assembly using multiple etch steps to form a pillar after forming a routing line.
  2. Lin,Charles W. C.; Wang,Chia Chung, Method of making a semiconductor chip assembly with a metal containment wall and a solder terminal.
  3. Lin,Charles W. C., Method of making a semiconductor chip assembly with a pillar and a routing line using multiple etch steps.
  4. Wang,Chia Chung; Lin,Charles W. C., Method of making a semiconductor chip assembly with a precision-formed metal pillar.
  5. Lin,Charles W. C., Method of making a semiconductor chip assembly with a press-fit ground plane.
  6. Lin,Charles W. C., Method of making a semiconductor chip assembly with a solder-attached ground plane.
  7. Wang,Chia Chung; Lin,Charles W. C., Method of making a semiconductor chip assembly with an interlocked contact terminal.
  8. Tziovaras,Georgios; Pophusen,Dirk; Gehrke,Hans Georg, Method of making metallized plastic moldings and their use.
  9. Islam, Shafidul; San Antonio, Romarico Santos, Partially patterned lead frames and methods of making and using the same in semiconductor packaging.
  10. Ramos, Mary Jean; San Antonio, Romarico Santos; Subagio, Anang, Partially patterned lead frames and methods of making and using the same in semiconductor packaging.
  11. Ramos, Mary Jean; Subagio, Anang; Guirit, Lynn Simporios; San Antonio, Romarico Santos, Partially patterned lead frames and methods of making and using the same in semiconductor packaging.
  12. San Antonio, Romarico S.; McKerreghan, Michael H.; Subagio, Anang; Toriaga, Allan C., Partially patterned lead frames and methods of making and using the same in semiconductor packaging.
  13. Wang,Chia Chung; Lin,Charles W. C., Semiconductor chip assembly with interlocked contact terminal.
  14. Lin,Charles W. C.; Wang,Chia Chung, Semiconductor chip assembly with metal containment wall and solder terminal.
  15. Lin,Charles W. C., Semiconductor chip assembly with pillar press-fit into ground plane.
  16. Wang,Chia Chung; Lin,Charles W. C., Semiconductor chip assembly with precision-formed metal pillar.
  17. Lin,Charles W. C., Semiconductor chip assembly with press-fit ground plane.
  18. Lin, Charles W. C., Semiconductor chip assembly with simultaneously electrolessly plated contact terminal and connection joint.
  19. Lin,Charles W. C., Semiconductor chip assembly with solder-attached ground plane.
  20. Noma, Takashi; Morita, Yuichi; Yamada, Hiroshi; Okada, Kazuo; Kitagawa, Katsuhiko; Okubo, Noboru; Ishibe, Shinzo; Shinogi, Hiroyuki, Semiconductor device and manufacturing method thereof.
  21. Noma, Takashi; Otsuka, Shigeki; Morita, Yuichi; Okada, Kazuo; Yamada, Hiroshi; Kitagawa, Katsuhiko; Okubo, Noboru; Ishibe, Shinzo; Shinogi, Hiroyuki, Semiconductor device and manufacturing method thereof.
  22. Kitagawa, Katsuhiko; Shinogi, Hiroyuki; Ishibe, Shinzo; Yamada, Hiroshi, Semiconductor device and method of manufacturing the same.
  23. Islam,Shafidul; San Antonio,Romarico Santos; Gultom,Lenny Christina, Taped lead frames and methods of making and using the same in semiconductor packaging.
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