초록 ▼

An improved manufacturing process and an improved device made by the process are described for forming via interconnects between metal layers in a multilevel metallization structure. This process essentially eliminates exploding vias due to vias extending beyond the edge of metal lines. The strong r

An improved manufacturing process and an improved device made by the process are described for forming via interconnects between metal layers in a multilevel metallization structure. This process essentially eliminates exploding vias due to vias extending beyond the edge of metal lines. The strong reaction is caused by the chemical interaction of metal lines beneath vias with reactants and/or reaction products associated with via fill. An insulating cap layer is deposited on the patterned and etched metal layer before depositing the interlevel dielectric layer above it. A two-step via etch process selectively removes portions of the cap layer within vias prior to via fill. The remaining cap layer within the vias covers, and thereby protects, otherwise vulnerable underlying metal from the damaging chemical interaction during via fill. Using this process, metal borders around vias can be reduced or eliminated, thereby increasing circuit packing density.

대표청구항 ▼

An improved manufacturing process and an improved device made by the process are described for forming via interconnects between metal layers in a multilevel metallization structure. This process essentially eliminates exploding vias due to vias extending beyond the edge of metal lines. The strong r

An improved manufacturing process and an improved device made by the process are described for forming via interconnects between metal layers in a multilevel metallization structure. This process essentially eliminates exploding vias due to vias extending beyond the edge of metal lines. The strong reaction is caused by the chemical interaction of metal lines beneath vias with reactants and/or reaction products associated with via fill. An insulating cap layer is deposited on the patterned and etched metal layer before depositing the interlevel dielectric layer above it. A two-step via etch process selectively removes portions of the cap layer within vias prior to via fill. The remaining cap layer within the vias covers, and thereby protects, otherwise vulnerable underlying metal from the damaging chemical interaction during via fill. Using this process, metal borders around vias can be reduced or eliminated, thereby increasing circuit packing density. use. 12. The road marking compound according to claim 1 comprising a styrenic block copolymer in which the styrenic block copolymer comprises a tetrablock copolymer having a styrene content of from 10-30 wt %. 13. A road marking compound according to claim 12 in which the styrene content is from 16-19 wt %. 14. A road marking compound according to claim 12 in which the block copolymer has a molecular weight from 50,000 g/mole to 500,000 g/mole. 15. A road marking compound according to claim 12 in which the styrenic blocks have a molecular weight from 4,000 g/mole to 35,000 g/mole. 16. A road marking compound according to claim 12 in which the styrenic blocks have a molecular weight from 6,000 g/mole to 20,000 g/mole. 17. A road marking compound according to claim 12 in which the unsaturated diene blocks have a molecular weight from 15,000 g/mole to 200,000 g/mole. 18. A road marking compound according to claim 12 in which the unsaturated diene blocks have a molecular weight from 15,000 g/mole to 150,000 g/mole.