초록 ▼

An architecture for registers and/or memory may provide a selectively disable payload portion. The architecture induced energy conservation. The architecture may include two or more payload portions for storage of payload data and a portion for storage of administrative data. Based on the contacts o

An architecture for registers and/or memory may provide a selectively disable payload portion. The architecture induced energy conservation. The architecture may include two or more payload portions for storage of payload data and a portion for storage of administrative data. Based on the contacts of the administrative data, certain payload portions may be enabled or disabled.

대표청구항 ▼

An architecture for registers and/or memory may provide a selectively disable payload portion. The architecture induced energy conservation. The architecture may include two or more payload portions for storage of payload data and a portion for storage of administrative data. Based on the contacts o

An architecture for registers and/or memory may provide a selectively disable payload portion. The architecture induced energy conservation. The architecture may include two or more payload portions for storage of payload data and a portion for storage of administrative data. Based on the contacts of the administrative data, certain payload portions may be enabled or disabled. d first converter is configured to provide said power in a steady state. 11. The power supply as recited in claim 8, wherein said control circuit is further configured to enable said second converter only in response to determining that said voltage at said output node is not within a predetermined range. 12. The power supply as recited in claim 8, wherein said control circuit is further configured to disable said second converter in response to determining that said output voltage at said output node is within said predetermined range. 13. The power supply as recited in claim 8, wherein said control circuit is further configured to alternately enable and disable said second converter in response to detecting a predetermined current through said second series inductor. 14. The power supply as recited in claim 8, wherein said second converter is a buck-derived fast response converter. 15. The power supply as recited in claim 8, wherein said predetermined range is a range of voltages between a positive percentage of said output voltage and a negative percentage of said output voltage. 16. A system comprising: a microprocessor; and a power supply coupled to said microprocesor, said power supply including: a first converter configured to provide power to an output node through a first series inductor; a second converter configured to provide power to said output node through a second series inductor, wherein said second series inductor has a smaller inductance than said first series inductor; and a control circuit coupled to said second converter and configured to selectively enable said second converter depending upon a voltage at said output node; wherein said second converter is characterized by a transient response time that is faster than a transient response time of said first converter. 17. The system as recited in claim 16, wherein said second converter is configured to respond to one or more transient voltage events at said output node. 18. The system as recited in claim 17, wherein said first converter is configured to provide said power in a steady state. 19. The system as recited in claim 16, wherein said control circuit is further configured to enable said second converter only in response to determining that said output voltage is not within a predetermined range. 20. The system as recited in claim 16, wherein said control circuit is further configured to disable said second converter in response to determining that said output voltage is within said predetermined range. 21. The system as recited in claim 16, wherein said control circuit is further configured to alternately enable and disable said second converter in response to detecting a predetermined current through said second series inductor. 22. The system as recited in claim 16, wherein said second converter is a buck-derived fast response converter. 23. The system as recited in claim 16, wherein said predetermined range is a range of voltages between a positive percentage of said output voltage at said output node and a negative percentage of said output voltage at said output node. 24. A power supply comprising: a first converter configured to provide DC power to an output node; a second converter configured to provide DC power to said output node in parallel with said first converter; wherein said second converter is characterized by a transient response time that is faster than a transient response time of said first converter; and a control circuit coupled to said second converter and configured to enable said second converter during one or more transient voltage events at said output node. 25. The power supply as recited in claim 24, wherein said first converter is configured to provide said DC power in a steady state. 26. The power supply as recited in claim 24, wherein said control circuit is further configured to enable said second converter only in response to determining that a voltage at said output node is not within a predete