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Endian-neutral loader for interpretive environment 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-009/45
  • G06F-009/44
출원번호 US-0118703 (1998-07-17)
발명자 / 주소
  • Adams, Phillip M.
출원인 / 주소
  • Novell, Inc.
대리인 / 주소
    Haynes and Boone, LLP
인용정보 피인용 횟수 : 13  인용 특허 : 27

초록

A method is disclosed for a endian correction at load time, thereby eliminating the need to perform multiple endian correction routines during execution. The method comprises obtaining a platform endian context corresponding to the processor; obtaining a operand endian context indicating the orderin

대표청구항

A method is disclosed for a endian correction at load time, thereby eliminating the need to perform multiple endian correction routines during execution. The method comprises obtaining a platform endian context corresponding to the processor; obtaining a operand endian context indicating the orderin

이 특허에 인용된 특허 (27)

  1. Adams Phillip M., Accelerator for interpretive environments.
  2. Sites Richard Lee (Menlo Park CA), Alternate execution and interpretation of computer program having code at unknown locations due to transfer instructions.
  3. Willard Pierre Mathias, Apparatus for delivering CPU independent data for little and big endian machines.
  4. Adams Phillip M., Burst-loading of instructions into processor cache by execution of linked jump instructions embedded in cache line size blocks.
  5. Asghar Saf ; Ireton Mark ; Bartkowiak John, CPU with DSP having decoder that detects and converts instruction sequences intended to perform DSP function into DSP f.
  6. Yin Chenwei J. (Richardson TX) Nail Richard C. (Plano TX) Izzi Louis J. (Plano TX) Chiu Edison H. (Richardson TX), Color palette device having big/little endian interfacing, systems and methods.
  7. Edmondson John H. (Cambridge MA) Biro Larry L. (Oakham MA), Combined write-operand queue and read-after-write dependency scoreboard.
  8. Trissel David Wesley, Computer instruction which generates multiple results of different data types to improve software emulation.
  9. Kummer David A. (Thousand Oaks CA) Rumer Robert T. (Camarillo CA), Computer system including a write protection circuit for preventing illegal write operations and a write poster with imp.
  10. Correnti Joseph A. (Boca Raton FL) Pipitone Ralph M. (Boynton Beach FL) Thomas Michael W. (Bellevue WA), Data processing system and method having selectable scheduler.
  11. Van Aken Jerry R. (Sugar Land TX) Yin Chenwei J. (Richardson TX), Flexible graphics interface device switch selectable big and little endian modes, systems and methods.
  12. Smith Alan J. (Berkeley CA), Instruction execution accelerator for a pipelined digital machine with virtual memory.
  13. Spear Dan (West Hollywood CA) Mayer Larry (Los Angeles CA), Memory management method.
  14. Larsen Larry D. (Raleigh NC) Nuechterlein David W. (Durham NC) O\Donnell Kim E. (Raleigh NC) Rogers Lee S. (Raleigh NC) Sartorius Thomas A. (Raleigh NC) Schultz Kenneth D. (Cary NC) Linzer Harry I. (, Method and apparatus for controlling operation of a cache memory during an interrupt.
  15. Tarsy Gregory (Scotts Valley CA) Woodard Michael J. (Fremont CA), Method and apparatus for cost-based heuristic instruction scheduling.
  16. Huck Kamla (Portland OR) Glew Andrew F. (Hillsboro OR) Rodgers Scott D. (Hillsboro OR), Method and apparatus for loading a segment register in a microprocessor capable of operating in multiple modes.
  17. Sandage David A. (Forest Grove OR) Stanley James C. (Portland OR) Hunt Stewart W. (Portland OR) Kunz Arland D. (Beaverton OR), Method and apparatus for sharing a common routine stored in a single virtual machine with other virtual machines operati.
  18. Horwat Waldemar, Object code structure and method for translation of architecture independent program implementations.
  19. Wilkinson Paul Amba ; Dieffenderfer James Warren ; Kogge Peter Michael ; Schoonover Nicholas Jerome, Parallel processing system having asynchronous SIMD processing.
  20. Hartung Michael H. (Tucson AZ) Nolta Arthur H. (Tucson AZ) Reed David G. (Tucson AZ), Roll mode for cached data storage.
  21. Stimac Gary A. (Houston TX) Crosswy William C. (Houston TX) Preston Stephen B. (Spring TX) Flannigan James S. (Cypress TX), Software emulation of bank-switched memory using a virtual DOS monitor and paged memory management.
  22. Gregor Steven L. (Endicott NY), Store queue for a tightly coupled multiple processor configuration with two-level cache buffer storage.
  23. Collins Robert W. (2404 NW. 4 Ave. Rochester MN 55901) Hoffman Roy L. (Rte. #2 Pine Island MN 55963) Loen Larry W. (2203 NW. 17 Ave. Rochester MN 55901) Mitchell Glen R. (Rte. #1 Pine Island MN 55963, Synchronizing mechanism for page replacement control.
  24. Denton James L. (Rochester MN) Eickemeyer Richard James (Rochester MN) Griffin Kevin Curtis (Rochester MN) Johnson Ross Evan (Rochester MN) Kunkel Steven Raymond (Rochester MN) Lipasti Mikko Herman (, System and method for increasing cache efficiency through optimized data allocation.
  25. Gregor Steven L. (Endicott NY) Iannucci Robert A. (Andover MA), System for synchronizing execution by a processing element of threads within a process using a state indicator.
  26. Kardach James (San Jose CA) Nguyen Cau (Milpitas CA), Transparent system interrupts with integrated extended memory addressing.
  27. Raman Srinivas (Folsom CA), Write back cache coherency module for systems with a write through cache supporting bus.

이 특허를 인용한 특허 (13)

  1. McGoogan, Sean; Gaster, Benedict; Shann, Richard, Bi-endian libraries.
  2. Lee,Jeong Ju, Computer system providing endian information and method of data transmission thereof.
  3. Bridges, Dick, Cross-platform software framework for embedded systems on data storage device.
  4. Nevill, Edward Colles, Data processing with native and interpreted program instruction words.
  5. Larsson, Fredrik; Werner, Bengt; Magnusson, Peter, Interpreter for executing computer programs and method for collecting statistics.
  6. Adiletta, Matthew J.; Wilkinson, Hugh; Kushlis, Robert J., Method and apparatus for implementing a bi-endian capable compiler.
  7. Adiletta, Matthew J; Wilkinson, Hugh; Kushlis, Robert J, Method and apparatus for implementing a bi-endian capable compiler.
  8. Brown,Alex; North,Geraint; Weigel,Frank Thomas; Knight,Gareth Anthony, Method and apparatus for performing native binding to execute native code.
  9. Loenko, Mikhail Yurievich, Optimizing code using a bi-endian compiler.
  10. Albert, Eric; Kosut, Alexei Elias; Watson, Matthew George; Zellers, Steve, Typed-data translation for platform independence.
  11. Albert, Eric; Kosut, Alexei Elias; Watson, Matthew George; Zellers, Steve, Typed-data translation for platform independence.
  12. Gschwind, Michael K.; Olsson, Brett, Virtualization in a bi-endian-mode processor architecture.
  13. Gschwind, Michael K.; Olsson, Brett, Virtualization in a bi-endian-mode processor architecture.
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