IPC분류정보
국가/구분 |
United States(US) Patent
등록
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국제특허분류(IPC7판) |
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출원번호 |
US-0916065
(2001-07-26)
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발명자
/ 주소 |
- Temple, Andrew B.
- Temple, Beva O.
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출원인 / 주소 |
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대리인 / 주소 |
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인용정보 |
피인용 횟수 :
3 인용 특허 :
19 |
초록
▼
A retractable, plastic enclosure (30) for row crops, ideally tomatoes, comprises a pair of plastic walls (33, 34) bordering the seedbed (22) that are supported by spaced-apart ribs (40, 42). Row crops between the closed walls are shielded from extreme conditions including frost, heavy rain, freeze,
A retractable, plastic enclosure (30) for row crops, ideally tomatoes, comprises a pair of plastic walls (33, 34) bordering the seedbed (22) that are supported by spaced-apart ribs (40, 42). Row crops between the closed walls are shielded from extreme conditions including frost, heavy rain, freeze, hail, and winds. The multi-ply, plastic walls are formed by folding a sheet of plastic. Arcuate ribs (40, 42) flexibly secure the walls in symmetric, spaced apart, parallel rows adjoining crops on either side of the raised seedbed. The walls may be yieldably drawn together or forced apart by drawstrings (82, 80). The ribs are formed from multiple separate strips (50, 52) that are stapled together and sandwich at least one wall layer. The drawstrings are routed between spaced-apart rib guides in a zigzag fashion. Tensioning of the lower drawstring closes the walls, sheltering the young row crops. The upper drawstring opens the walls.
대표청구항
▼
A retractable, plastic enclosure (30) for row crops, ideally tomatoes, comprises a pair of plastic walls (33, 34) bordering the seedbed (22) that are supported by spaced-apart ribs (40, 42). Row crops between the closed walls are shielded from extreme conditions including frost, heavy rain, freeze,
A retractable, plastic enclosure (30) for row crops, ideally tomatoes, comprises a pair of plastic walls (33, 34) bordering the seedbed (22) that are supported by spaced-apart ribs (40, 42). Row crops between the closed walls are shielded from extreme conditions including frost, heavy rain, freeze, hail, and winds. The multi-ply, plastic walls are formed by folding a sheet of plastic. Arcuate ribs (40, 42) flexibly secure the walls in symmetric, spaced apart, parallel rows adjoining crops on either side of the raised seedbed. The walls may be yieldably drawn together or forced apart by drawstrings (82, 80). The ribs are formed from multiple separate strips (50, 52) that are stapled together and sandwich at least one wall layer. The drawstrings are routed between spaced-apart rib guides in a zigzag fashion. Tensioning of the lower drawstring closes the walls, sheltering the young row crops. The upper drawstring opens the walls. ormation, said cache memory including an isochronous cache that is reserved for storing only said isochronous data, said isochronous cache being inaccessible to non-isochronous processes for storing non-isochronous data, said isochronous cache being reconfigurable by a cache manager and a cache controller into separate cache channels that each correspond to a different respective isochronous process; and a processor coupled to said cache memory for utilizing said priority information from said cache memory. 2. A system for optimizing processor operations, comprising: a transmission source configured provide priority information for use by an electronic device, said priority information including isochronous data for performing a time-sensitive isochronous process, a cache memory coupled to said transmission source and configured for temporarily storing said priority information, said cache memory comprising an isochronous cache including a cache controller, one or more cache channels, and cache registers, wherein said isochronous cache is reconfigurable by a cache manager and said cache controller into separate cache channels that each correspond to a different respective isochronous process; and a processor coupled to said cache memory for utilizing said priority information from said cache memory. 3. The system of claim 2 wherein said cache registers include at least one of a total channels field, an allocated channels field, a total memory field, an allocated memory field, and one or more channel registers. 4. The system of claim 3 wherein said channel registers include at least one of a process identifier field and a required memory field. 5. The system of claim 3 wherein a cache manager initiates a channel setup procedure after receiving a channel setup request from a requesting entity to configure a new cache channel for an isochronous process, said channel setup request including at least one of a data transfer size, an isochronous process identifier, a transmission bus channel number for mapping to a corresponding isochronous cache channel number, and a transfer direction indicator. 6. The system of claim 5 wherein said cache manager allocates said new cache channel only after determining that said new cache channel is available by analyzing said total channels field and said allocated channels field in said cache registers. 7. The system of claim 5 wherein said cache manager allocates said new cache channel only after determining that a sufficient memory space is available for said new cache channel by analyzing said total memory field and said allocated memory field in said cache registers, and said required memory field in a corresponding channel register. 8. The system of claim 5 wherein said cache manager transmits a new channel allocation message to said cache controller, said cache controller responsively reconfiguring said isochronous cache to include said new cache channel. 9. The system of claim 8 wherein said cache manager returns a setup completion message and a cache channel number to said requesting entity, said cache manager also updating said cache registers to account for said new cache channel. 10. The system of claim 2 wherein said cache controller begins a data transfer operation by detecting an isochronous indicator. 11. The system of claim 10 wherein said cache controller determines that said data transfer operation is a send operation, and responsively invokes send logic that arbitrates for access to said system bus and then transmits said isochronous data from said isochronous cache onto said system bus. 12. The system of claim 10 wherein said cache controller determines that said data transfer operation is a receive operation, responsively utilizes a mapping technique to identify an allocated cache channel in said isochronous cache, and then transfers said isochronous data from said system bus into said allocated isochronous channel. 13. The system of claim 2 wherein said processor be
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